coreboot-gerrit September 2023

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[XS] Change in coreboot[master]: acpi/acpi.c: Accomodate 64bit MMCONF base in MCFG table
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77539?usp=email ) Change subject: acpi/acpi.c: Accomodate 64bit MMCONF base in MCFG table ...................................................................... acpi/acpi.c: Accomodate 64bit MMCONF base in MCFG table Allow the use of 64bit MMCONF base in MCFG table. Previously only 32 bits were utilized for MMCONF base, while the remaining 32bits were reserved & held value of zero as evident from MCFG table disassembly. This commit entails updating the 'base_address' field in the 'mmconfig' structure to 64 bits and removing the 'base_reserved' field. TEST=Confirmed the functionality of the 64bit MMCONF base in the MCFG table disassembly below Signature : "MCFG" Table Length : 0000003C Revision : 01 Checksum : BD Oem ID : "COREv4" Oem Table ID : "COREBOOT" Oem Revision : 00000000 Asl Compiler ID : "CORE" Asl Compiler Revision : 20230628 Reserved : 0000000000000000 Base Address : 0000001010000000 Segment Group Number : 0000 Start Bus Number : 00 End Bus Number : FF Reserved : 00000000 Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77539 Reviewed-by: Tim Wawrzynczak <inforichland(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e30b7d3..e357f6a 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -117,12 +117,11 @@ return CB_SUCCESS; } -static int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, +static int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u64 base, u16 seg_nr, u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; - mmconfig->base_reserved = 0; mmconfig->pci_segment_group_number = seg_nr; mmconfig->start_bus_number = start; mmconfig->end_bus_number = end; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 33bd735..3a7c99c 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -217,8 +217,7 @@ } __packed acpi_tpm2_t; typedef struct acpi_mcfg_mmconfig { - u32 base_address; - u32 base_reserved; + u64 base_address; u16 pci_segment_group_number; u8 start_bus_number; u8 end_bus_number; -- To view, visit https://review.coreboot.org/c/coreboot/+/77539?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f4bc727c3239bf941e1a09bc277ed66ae6b0185 Gerrit-Change-Number: 77539 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp image
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Varshit Pandya. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76496?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp image ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Needs a manual rebase. -- To view, visit https://review.coreboot.org/c/coreboot/+/76496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I639fb1e911a7449d0db0d2bfcfbb6f4f225b0cef Gerrit-Change-Number: 76496 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Sep 2023 21:08:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/onyx: Add minimal code for onyx compilation
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77601?usp=email ) Change subject: mb/amd/onyx: Add minimal code for onyx compilation ...................................................................... mb/amd/onyx: Add minimal code for onyx compilation Change-Id: I25807e116869d1bd7b8324525bc5ae1691e072e4 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77601 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/amd/onyx/Kconfig A src/mainboard/amd/onyx/Kconfig.name A src/mainboard/amd/onyx/board_info.txt A src/mainboard/amd/onyx/devicetree.cb A src/mainboard/amd/onyx/dsdt.asl 5 files changed, 36 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/onyx/Kconfig b/src/mainboard/amd/onyx/Kconfig new file mode 100644 index 0000000..ce1b980 --- /dev/null +++ b/src/mainboard/amd/onyx/Kconfig @@ -0,0 +1,14 @@ +if BOARD_AMD_ONYX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_GENOA + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "amd/onyx" + +config MAINBOARD_PART_NUMBER + default "Onyx" + +endif diff --git a/src/mainboard/amd/onyx/Kconfig.name b/src/mainboard/amd/onyx/Kconfig.name new file mode 100644 index 0000000..0dc99a7 --- /dev/null +++ b/src/mainboard/amd/onyx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_ONYX + bool "Onyx" diff --git a/src/mainboard/amd/onyx/board_info.txt b/src/mainboard/amd/onyx/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/onyx/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb new file mode 100644 index 0000000..5f447b2 --- /dev/null +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/amd/genoa + + device domain 0 on + end + +end diff --git a/src/mainboard/amd/onyx/dsdt.asl b/src/mainboard/amd/onyx/dsdt.asl new file mode 100644 index 0000000..ecfe7a5 --- /dev/null +++ b/src/mainboard/amd/onyx/dsdt.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ +) +} /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/77601?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25807e116869d1bd7b8324525bc5ae1691e072e4 Gerrit-Change-Number: 77601 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd/genoa: Add minimal viable code for compilation
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76495?usp=email ) Change subject: soc/amd/genoa: Add minimal viable code for compilation ...................................................................... soc/amd/genoa: Add minimal viable code for compilation This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with amd linker script hooked up. Default to 64bit code as that will be a sensible default for this platform (high memory access required for RAS setup). Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/soc/amd/genoa/Kconfig A src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/chip.c A src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/iomap.h A src/soc/amd/genoa/include/soc/southbridge.h A src/soc/amd/genoa/romstage.c A src/soc/amd/genoa/timer.c 8 files changed, 167 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Martin L Roth: Looks good to me, approved diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig new file mode 100644 index 0000000..f799ac18 --- /dev/null +++ b/src/soc/amd/genoa/Kconfig @@ -0,0 +1,73 @@ +config SOC_AMD_GENOA + bool + +if SOC_AMD_GENOA + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select HAVE_EXP_X86_64_SUPPORT + select NO_ECAM_MMCONF_SUPPORT + select NO_MONOTONIC_TIMER + select RESET_VECTOR_IN_RAM + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_NONCAR + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select UNKNOWN_TSC_RATE + +config USE_EXP_X86_64_SUPPORT + default y + +config EARLY_RESERVED_DRAM_BASE + hex + default 0x7000000 + help + This variable defines the base address of the DRAM which is reserved + for usage by coreboot in early stages (i.e. before ramstage is up). + This memory gets reserved in BIOS tables to ensure that the OS does + not use it, thus preventing corruption of OS memory in case of S3 + resume. + +config EARLYRAM_BSP_STACK_SIZE + hex + default 0x1000 + +config PSP_APOB_DRAM_ADDRESS + hex + default 0x7001000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_DRAM_SIZE + hex + default 0x20000 + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x1600 + help + Increase this value if preram cbmem console is getting truncated + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x10000 + help + Sets the size of the bootblock stage that should be loaded in DRAM. + This variable controls the DRAM allocation size in linker script + for bootblock stage. + +config ROMSTAGE_ADDR + hex + default 0x7040000 + help + Sets the address in DRAM where romstage should be loaded. + +config ROMSTAGE_SIZE + hex + default 0x80000 + help + Sets the size of DRAM allocation for romstage in linker script. + +endif diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc new file mode 100644 index 0000000..01b1965 --- /dev/null +++ b/src/soc/amd/genoa/Makefile.inc @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_SOC_AMD_GENOA),y) + +bootblock-y += early_fch.c + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +CPPFLAGS_common += -I$(src)/soc/amd/genoa/include + +endif diff --git a/src/soc/amd/genoa/chip.c b/src/soc/amd/genoa/chip.c new file mode 100644 index 0000000..cbe3e13 --- /dev/null +++ b/src/soc/amd/genoa/chip.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations soc_amd_genoa_ops = { NULL }; diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c new file mode 100644 index 0000000..dcb390b --- /dev/null +++ b/src/soc/amd/genoa/early_fch.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/espi.h> +#include <amdblocks/lpc.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/aoac.h> +#include <amdblocks/pmlib.h> +#include <amdblocks/uart.h> +#include <soc/southbridge.h> + +/* Before console init */ +void fch_pre_init(void) +{ + +} + +/* After console init */ +void fch_early_init(void) +{ + +} diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h new file mode 100644 index 0000000..076938e --- /dev/null +++ b/src/soc/amd/genoa/include/soc/iomap.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_IOMAP_H +#define AMD_GENOA_IOMAP_H + +#define SPI_BASE_ADDRESS 0xfec10000 + +/* @Todo : Check these values for Genoa */ + +/* I/O Ranges */ +#define ACPI_IO_BASE 0x0400 +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) + +/* FCH AL2AHB Registers */ +#define ALINK_AHB_ADDRESS 0xfedc0000 + +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 + +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_UART2_BASE 0xfedce000 + +#endif /* AMD_GENOA_IOMAP_H */ diff --git a/src/soc/amd/genoa/include/soc/southbridge.h b/src/soc/amd/genoa/include/soc/southbridge.h new file mode 100644 index 0000000..95c054c --- /dev/null +++ b/src/soc/amd/genoa/include/soc/southbridge.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_GENOA_SOUTHBRIDGE_H +#define AMD_GENOA_SOUTHBRIDGE_H + +#include <soc/iomap.h> + + +void fch_pre_init(void); +void fch_early_init(void); + +#endif /* AMD_GENOA_SOUTHBRIDGE_H */ diff --git a/src/soc/amd/genoa/romstage.c b/src/soc/amd/genoa/romstage.c new file mode 100644 index 0000000..f4c5584 --- /dev/null +++ b/src/soc/amd/genoa/romstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <romstage_common.h> +#include <halt.h> + +void __noreturn romstage_main(void) +{ + /* Needed for __noreturn */ + halt(); +} diff --git a/src/soc/amd/genoa/timer.c b/src/soc/amd/genoa/timer.c new file mode 100644 index 0000000..9054ffd --- /dev/null +++ b/src/soc/amd/genoa/timer.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Gerrit-Change-Number: 76495 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mainboard/google/skyrim: Enable MP2 FW loading
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72118?usp=email ) Change subject: mainboard/google/skyrim: Enable MP2 FW loading ...................................................................... mainboard/google/skyrim: Enable MP2 FW loading This board will use custom MP2 FW to dump the contents of the STB when the SOC fails to enter/exit S0i3. Enable `PSP_LOAD_MP2_FW` by default. BUG=b:259554520 TEST=Built and ran on skyrim device, verified that MP2 FW loads. Change-Id: I4222521d01e2c98708f0e5b6693a8aee9e59edf2 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72118 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/amdfw.cfg 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 44ecfc4..53dfd53 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -71,7 +71,7 @@ config PSP_LOAD_MP2_FW prompt "Load MP2 Firmware" depends on CHROMEOS - default n + default y config HAVE_SPL_FILE bool diff --git a/src/mainboard/google/skyrim/amdfw.cfg b/src/mainboard/google/skyrim/amdfw.cfg index 01e36ab..63aed0c 100644 --- a/src/mainboard/google/skyrim/amdfw.cfg +++ b/src/mainboard/google/skyrim/amdfw.cfg @@ -29,11 +29,11 @@ DMCUB_FILE TypeId0x71_DmcubFw_MDN.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2_MDN.sbin TA_IKEK_FILE TypeId0x8D_IkekTa_MDN.bin -PSP_MP2FW0_FILE 3rdparty/blobs/mainboard/google/skyrim/TypeId0x25_Mp2Fw_MDN_AD03.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_MDN.sbin # BDT PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_MDN_Lpddr5Imem1.csbin PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_MDN_Lpddr5Dmem1.csbin PSP_PMUI_FILE_SUB0_INS2 TypeId0x64_Appb_MDN_Lpddr5Imem2.csbin PSP_PMUD_FILE_SUB0_INS2 TypeId0x65_Appb_MDN_Lpddr5Dmem2.csbin -PSP_MP2CFG_FILE 3rdparty/blobs/mainboard/google/skyrim/TypeId0x6A_ConfigFile.sbin +PSP_MP2CFG_FILE TypeId0x6a_Mp2FwConfig_MDN.sbin -- To view, visit https://review.coreboot.org/c/coreboot/+/72118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4222521d01e2c98708f0e5b6693a8aee9e59edf2 Gerrit-Change-Number: 72118 Gerrit-PatchSet: 8 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77541?usp=email ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Update amd_blobs submodule to upstream master Updating from commit id 6a1e1457afdd: 2023-08-18 16:32:27 -0600 - (Add GenoaPI 1.0.0.4 blobs) to commit id 591d5fb62cbb: 2023-08-21 13:57:09 -0600 - (mendocino: Update MP2 FW to 0A.0D.00.06) This brings in 1 new commit: 591d5fb mendocino: Update MP2 FW to 0A.0D.00.06 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77541 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 6a1e145..591d5fb 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 6a1e1457afddf49e53bfa4f422e7fd42f9db6e49 +Subproject commit 591d5fb62cbb8875d1a1004b672a2a293c6fb697 -- To view, visit https://review.coreboot.org/c/coreboot/+/77541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Gerrit-Change-Number: 77541 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/cpu: Only show MP PPI option when meaningful
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63759?usp=email ) Change subject: soc/intel/cpu: Only show MP PPI option when meaningful ...................................................................... soc/intel/cpu: Only show MP PPI option when meaningful Older FSP releases don't have an option to do MP init via PPI, so it should not be visible. Change-Id: I74b4bd5dd72980b859763e89ead7d7f619321e66 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63759 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 316ec40..8c14cb2 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -119,8 +119,8 @@ config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" - default y if MP_SERVICES_PPI - default n + default y + depends on MP_SERVICES_PPI help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/63759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74b4bd5dd72980b859763e89ead7d7f619321e66 Gerrit-Change-Number: 63759 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kane Chen, Kapil Porwal, Tarun, Wentao Qin. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77520?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/rex/var/screebo: Set `SAGV_POINTS_0_1_2` to avoid hang ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77520/comment/14a05512_99117cb6 : PS4, Line 11: Before root cause, this is a short term workaround to unblock function test. Please wrap. -- To view, visit https://review.coreboot.org/c/coreboot/+/77520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0947815ab79b470d2ae922cffdd8250c60cf1afd Gerrit-Change-Number: 77520 Gerrit-PatchSet: 4 Gerrit-Owner: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 21:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Add `rex4es_ec_ish` variant
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77358?usp=email ) Change subject: mb/google/rex: Add `rex4es_ec_ish` variant ...................................................................... mb/google/rex: Add `rex4es_ec_ish` variant This patch creates rex ES variant with EC ISH enabled. BUG=b:296886409 TEST=Able to build and boot rex4es_ec_ish variant. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I2b1cdb8cffd66badd90a7bf9825d9decb07941a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77358 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name 2 files changed, 13 insertions(+), 4 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index cc15b7b..78dc780 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -56,6 +56,11 @@ select DRIVERS_SOUNDWIRE_CS42L42 select DRIVERS_SOUNDWIRE_MAX98363 +config BOARD_GOOGLE_MODEL_REX_EC_ISH + def_bool n + select BOARD_GOOGLE_MODEL_REX + select SOC_INTEL_STORE_ISH_FW_VERSION + config BOARD_GOOGLE_MODEL_SCREEBO def_bool n select BOARD_GOOGLE_BASEBOARD_REX @@ -117,8 +122,8 @@ default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb" config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish-debug-fsp.fmd" if CHROMEOS && BOARD_GOOGLE_REX_EC_ISH && BUILDING_WITH_DEBUG_FSP - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish.fmd" if CHROMEOS && BOARD_GOOGLE_REX_EC_ISH + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish-debug-fsp.fmd" if CHROMEOS && BOARD_GOOGLE_MODEL_REX_EC_ISH && BUILDING_WITH_DEBUG_FSP + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish.fmd" if CHROMEOS && BOARD_GOOGLE_MODEL_REX_EC_ISH default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS @@ -134,6 +139,7 @@ default "Rex" if BOARD_GOOGLE_REX0 default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH default "Rex4ES" if BOARD_GOOGLE_REX4ES + default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH default "Screebo" if BOARD_GOOGLE_SCREEBO default "Screebo4ES" if BOARD_GOOGLE_SCREEBO4ES default "Karis" if BOARD_GOOGLE_KARIS diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index fc9a477..6119169 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -22,8 +22,7 @@ config BOARD_GOOGLE_REX_EC_ISH bool "-> Rex EC ISH" - select BOARD_GOOGLE_MODEL_REX - select SOC_INTEL_STORE_ISH_FW_VERSION + select BOARD_GOOGLE_MODEL_REX_EC_ISH config BOARD_GOOGLE_OVIS bool "-> Ovis" @@ -36,3 +35,7 @@ config BOARD_GOOGLE_REX4ES bool "-> Rex4ES" select BOARD_GOOGLE_MODEL_REX + +config BOARD_GOOGLE_REX4ES_EC_ISH + bool "-> Rex4ES EC ISH" + select BOARD_GOOGLE_MODEL_REX_EC_ISH -- To view, visit https://review.coreboot.org/c/coreboot/+/77358?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b1cdb8cffd66badd90a7bf9825d9decb07941a8 Gerrit-Change-Number: 77358 Gerrit-PatchSet: 6 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: google/puff: Enable ASPM of RTL8111H
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Alexis Savery, Edward O'Callaghan, Karthik Ramasubramanian. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77570?usp=email ) Change subject: google/puff: Enable ASPM of RTL8111H ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I129dfd79e8112191453be513b2e3a260429b3030 Gerrit-Change-Number: 77570 Gerrit-PatchSet: 2 Gerrit-Owner: Alexis Savery <asavery(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Alexis Savery <asavery(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 21:02:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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