coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/cannonlake/Kconfig: Deduplicate selections
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Felix Singer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77447?usp=email ) Change subject: soc/intel/cannonlake/Kconfig: Deduplicate selections ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7 Gerrit-Change-Number: 77447 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 01 Sep 2023 21:49:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoC
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Felix Singer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77446?usp=email ) Change subject: soc/intel/cannonlake/Makefile.inc: Remove dead code of CNL SoC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53cd9d53b01e26f530684aa9c404f50b305c1f54 Gerrit-Change-Number: 77446 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 01 Sep 2023 21:43:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: drivers/mrc_cache: Fix extra space at the beginning of line
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77594?usp=email ) Change subject: drivers/mrc_cache: Fix extra space at the beginning of line ...................................................................... drivers/mrc_cache: Fix extra space at the beginning of line Change-Id: Ic49cb6c67aa707efa6495788137b550683008868 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77594 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/drivers/mrc_cache/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Martin L Roth: Looks good to me, approved Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 7111153..22d1416 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -27,7 +27,7 @@ help MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT. If a platform requires MRC settings written to NVRAM later than - normal, select this item. This will cause the write to occur at + normal, select this item. This will cause the write to occur at BS_OS_RESUME_CHECK-ENTRY. config MRC_STASH_TO_CBMEM -- To view, visit https://review.coreboot.org/c/coreboot/+/77594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic49cb6c67aa707efa6495788137b550683008868 Gerrit-Change-Number: 77594 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA device
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77576?usp=email ) Change subject: soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA device ...................................................................... soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA device Add SA_DEV_SLOT_GNA definition to SoCs missing it, so the name resolves properly. TEST=tested with rest of patch train Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77576 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/include/soc/pci_devs.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/include/soc/pci_devs.h 6 files changed, 15 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 7f24032..8b32b96 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -94,6 +94,7 @@ case SA_DEVFN_TBT2: return "TRP2"; case SA_DEVFN_TBT3: return "TRP3"; case SA_DEVFN_IPU: return "IPU0"; + case SA_DEVFN_GNA: return "GNA"; case SA_DEVFN_DPTF: return "TCPU"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c index 567dccb..8cf982a 100644 --- a/src/soc/intel/jasperlake/chip.c +++ b/src/soc/intel/jasperlake/chip.c @@ -67,6 +67,7 @@ case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_IPU: return "IPU0"; case PCH_DEVFN_ISH: return "ISHB"; + case SA_DEVFN_GNA: return "GNA"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h index f6c4fc5..e327645 100644 --- a/src/soc/intel/jasperlake/include/soc/pci_devs.h +++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h @@ -30,6 +30,10 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) +#define SA_DEV_SLOT_IPU 0x05 +#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) +#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) + #define SA_DEV_SLOT_TBT 0x07 #define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) #define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) @@ -40,9 +44,9 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) -#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 79a2452..954c32b 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -83,6 +83,7 @@ case PCI_DEVFN_TBT3: return "TRP3"; case PCI_DEVFN_IPU: return "IPU0"; case PCI_DEVFN_ISH: return "ISHB"; + case PCI_DEVFN_GNA: return "GNA"; case PCI_DEVFN_XHCI: return "XHCI"; case PCI_DEVFN_I2C0: return "I2C0"; case PCI_DEVFN_I2C1: return "I2C1"; diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 242ec98..15281c8 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -83,6 +83,7 @@ case SA_DEVFN_TBT2: return "TRP2"; case SA_DEVFN_TBT3: return "TRP3"; case SA_DEVFN_IPU: return "IPU0"; + case SA_DEVFN_GNA: return "GNA"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index 7a9ea32..d93c97f 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -57,6 +57,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) + #define SA_DEV_SLOT_TMT 0x0A #define SA_DEVFN_TMT _SA_DEVFN(TMT) #define SA_DEV_TMT _SA_DEV(TMT) -- To view, visit https://review.coreboot.org/c/coreboot/+/77576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31c8b14e5083fc8e212a4e32330125fa72696c73 Gerrit-Change-Number: 77576 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/common/acpi: Add stub for GNA scoring accelerator
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77528?usp=email ) Change subject: soc/intel/common/acpi: Add stub for GNA scoring accelerator ...................................................................... soc/intel/common/acpi: Add stub for GNA scoring accelerator Allows boards which enable the GNA device to provide an attachment point for the OS drivers. TEST=tested with rest of patch train Change-Id: I3398eefb80e4407594883dd39128cd7885105ac3 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77528 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- A src/soc/intel/common/block/acpi/acpi/gna.asl 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/acpi/acpi/gna.asl b/src/soc/intel/common/block/acpi/acpi/gna.asl new file mode 100644 index 0000000..d5ad4f7 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/gna.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* GNA Scoring Accelerator - Device 08, Function 0 */ +Device (GNA) +{ + Name (_ADR, 0x00080000) + Name (_DDN, "GNA Scoring Accelerator") +} -- To view, visit https://review.coreboot.org/c/coreboot/+/77528?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3398eefb80e4407594883dd39128cd7885105ac3 Gerrit-Change-Number: 77528 Gerrit-PatchSet: 6 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Rename crashlog macros
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77236?usp=email ) Change subject: soc/intel/common: Rename crashlog macros ...................................................................... soc/intel/common: Rename crashlog macros Remove MAILBOX word from CPU_CRASHLOG_MAILBOX_WAIT_STALL and CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT macros, because they can be used for other interface as well. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I62b04fa4b05c427db494a536ca6504db02dfeb68 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77236 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h 2 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 5b098bb..fa36033 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -114,13 +114,13 @@ do { cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr); - udelay(CPU_CRASHLOG_MAILBOX_WAIT_STALL); + udelay(CPU_CRASHLOG_WAIT_STALL); stall_cnt++; } while ((cl_mailbox_interface.fields.busy == 1) - && stall_cnt < CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT); + && stall_cnt < CPU_CRASHLOG_WAIT_TIMEOUT); if ((cl_mailbox_interface.fields.busy == 1) - && (stall_cnt >= CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT)) { + && (stall_cnt >= CPU_CRASHLOG_WAIT_TIMEOUT)) { printk(BIOS_ERR, "CPU crashlog mailbox timed out.\n"); return 0; } diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index ceaa9f1..23d4861 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -17,8 +17,8 @@ /* CPU CrashLog Mailbox commands */ #define CPU_CRASHLOG_CMD_DISABLE 0 #define CPU_CRASHLOG_CMD_CLEAR 2 -#define CPU_CRASHLOG_MAILBOX_WAIT_STALL 1 -#define CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT 1000 +#define CPU_CRASHLOG_WAIT_STALL 1 +#define CPU_CRASHLOG_WAIT_TIMEOUT 1000 #define CPU_CRASHLOG_DISC_TAB_GUID_VALID 0x1600 #define CRASHLOG_SIZE_DEBUG_PURPOSE 0x640 -- To view, visit https://review.coreboot.org/c/coreboot/+/77236?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62b04fa4b05c427db494a536ca6504db02dfeb68 Gerrit-Change-Number: 77236 Gerrit-PatchSet: 6 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Skip crashlog region with metadata tag
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76834?usp=email ) Change subject: soc/intel/meteorlake: Skip crashlog region with metadata tag ...................................................................... soc/intel/meteorlake: Skip crashlog region with metadata tag Region with metadata tag contains information about BDF entry for SOC PMC SRAM and IOE SRAM. We don't need to parse this as we already define BDFs in soc/pci_devs.h for these SRAMs. Also we need to skip to region as it does not contain any crashlog data. BUG=b:262501347 TEST=Able to build google/rex. Able to trigger crashlog and decode correctly. Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76834 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/crashlog.c 1 file changed, 12 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 9d3c5d6..cf05b24 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -127,8 +127,19 @@ if (!descriptor_table.regions[i].bits.size) continue; - + /* + * Region with metadata TAG contains information about BDF entry for SOC PMC SRAM + * and IOE SRAM. We don't need to parse this as we already define BDFs in + * soc/pci_devs.h for these SRAMs. Also we need to skip this region as it does not + * contain any crashlog data. + */ if (descriptor_table.regions[i].bits.assign_tag == + CRASHLOG_DESCRIPTOR_TABLE_TAG_META) { + pmc_crashLog_size -= descriptor_table.regions[i].bits.size * + sizeof(u32); + printk(BIOS_DEBUG, "Found metadata tag. PMC crashlog size adjusted to: 0x%x\n", + pmc_crashLog_size); + } else if (descriptor_table.regions[i].bits.assign_tag == CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC) { if (cl_copy_data_from_sram(pmc_sram_base, -- To view, visit https://review.coreboot.org/c/coreboot/+/76834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890 Gerrit-Change-Number: 76834 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Add metadata tag definition for crashlog
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76833?usp=email ) Change subject: soc/intel/common: Add metadata tag definition for crashlog ...................................................................... soc/intel/common: Add metadata tag definition for crashlog When parsing descriptor table the record can have tag type = 7. This tag contains metadata depending on SOC. The platform may choose to parse it based on implementation of crashlog. BUG=b:262501347 TEST=Able to build google/rex. Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76833 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/crashlog.h 1 file changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index 91e8edd..ceaa9f1 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -25,9 +25,18 @@ #define INVALID_CRASHLOG_RECORD 0xdeadbeef -/* Tag field definitions */ +/* + * Tag field definitions. + * Each region pointed by the descriptor table contains TAG information. This TAG information + * is used to identify the type of SRAM the region belongs to, for example: + * - TAG 0 represents the SoC PMC region + * - TAG 1 represents the IOE PMC region + * - TAG 7 represents a special case aka metadata information. This metadata information can be + * SoC specific too. + */ #define CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC 0x0 #define CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE 0x1 +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_META 0x7 /* PMC crashlog discovery structs */ typedef union { -- To view, visit https://review.coreboot.org/c/coreboot/+/76833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2 Gerrit-Change-Number: 76833 Gerrit-PatchSet: 7 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76333?usp=email ) ( 18 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records ...................................................................... soc/intel/meteorlake: Validate CPU crashlog discovery table and records CPU crashlog discovery table and crashlog record is considered invalid if first 32bits of the table is either 0x0 (no crashlog) or 0xdeadbeef (invalid crashlog). Crashlog record is considered consumed if bit 31 is set. So in this case stop processing the subsequent records. BUG=b:289600699 TEST=Able to build and verified invalid records are skipped on google/rex. Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76333 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/crashlog.c 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 219c7e8..9d3c5d6 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -12,6 +12,8 @@ #include <soc/pci_devs.h> #include <string.h> +#define CRASHLOG_CONSUMED_MASK BIT(31) + /* global crashLog info */ static bool m_pmc_crashLog_support; static bool m_pmc_crashLog_present; @@ -364,6 +366,11 @@ return offset; } +static bool is_crashlog_data_valid(u32 dw0) +{ + return (dw0 != 0x0 && dw0 != INVALID_CRASHLOG_RECORD); +} + static bool cpu_cl_gen_discovery_table(void) { u32 bar_addr = 0, disc_tab_addr = 0; @@ -373,6 +380,11 @@ return false; disc_tab_addr = bar_addr + get_disc_table_offset(); + + u32 dw0 = read32((u32 *)disc_tab_addr); + if (!is_crashlog_data_valid(dw0)) + return false; + memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) + ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32)); @@ -381,7 +393,18 @@ int cur_offset = 0; for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { - cur_offset = 8 + 24*i; + cur_offset = 8 + 24 * i; + + dw0 = read32((u32 *)disc_tab_addr + cur_offset); + if (!is_crashlog_data_valid(dw0)) + continue; + + if (dw0 & CRASHLOG_CONSUMED_MASK) { + printk(BIOS_DEBUG, "cpu crashlog records already consumed." + "id: 0x%x dw0: 0x%x\n", i, dw0); + break; + } + cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr + cur_offset)) + ((u64)read32((u32 *) (disc_tab_addr + cur_offset + 4)) << 32)); -- To view, visit https://review.coreboot.org/c/coreboot/+/76333?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6 Gerrit-Change-Number: 76333 Gerrit-PatchSet: 20 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/meteorlake: Adjust discovery table offset based on CPUID
by Martin L Roth (Code Review) 01 Sep '23

01 Sep '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76400?usp=email ) Change subject: soc/intel/meteorlake: Adjust discovery table offset based on CPUID ...................................................................... soc/intel/meteorlake: Adjust discovery table offset based on CPUID CPUID CPUID_METEORLAKE_B0 onwards the discovery table offset needs to be left-shifted by 3. Reference: EDS Vol 1 (640228) BUG=b:289600699 TEST=Able to boot google/rex with crashlog enabled. Change-Id: I90647fb6190a52b42298398263978beaf931b035 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76400 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/crashlog.c 1 file changed, 14 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 2e3c97a..219c7e8 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -2,6 +2,8 @@ #include <arch/bert_storage.h> #include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/cpu_ids.h> #include <device/pci_ops.h> #include <intelblocks/crashlog.h> #include <intelblocks/pmc_ipc.h> @@ -351,6 +353,17 @@ return true; } +static u32 get_disc_table_offset(void) +{ + u32 offset = cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; + if (cpu_get_cpuid() >= CPUID_METEORLAKE_B0) { + offset <<= 3; + printk(BIOS_DEBUG, "adjusted cpu discovery table offset: 0x%x\n", offset); + } + + return offset; +} + static bool cpu_cl_gen_discovery_table(void) { u32 bar_addr = 0, disc_tab_addr = 0; @@ -359,16 +372,10 @@ if (!bar_addr) return false; - disc_tab_addr = bar_addr + - cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset; + disc_tab_addr = bar_addr + get_disc_table_offset(); memset(&cpu_cl_disc_tab, 0, sizeof(cpu_crashlog_discovery_table_t)); - - printk(BIOS_DEBUG, "cpu discovery table offset: 0x%x\n", - cpu_cl_devsc_cap.discovery_data.fields.discovery_table_offset); - cpu_cl_disc_tab.header.data = ((u64)read32((u32 *)disc_tab_addr) + ((u64)read32((u32 *)(disc_tab_addr + 4)) << 32)); - printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer count: 0x%x\n", cpu_cl_disc_tab.header.fields.count); -- To view, visit https://review.coreboot.org/c/coreboot/+/76400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90647fb6190a52b42298398263978beaf931b035 Gerrit-Change-Number: 76400 Gerrit-PatchSet: 17 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: merged

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coreboot-gerrit September 2023