coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

1 participants
3824 discussions

[XL] Change in coreboot[master]: soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Tim Crawford, Werner Zeh. Hello Eran Mitrani, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Tim Crawford, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77582?usp=email to look at the new patch set (#3). Change subject: soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB ...................................................................... soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB Windows expects the GPIO device to be under \_SB, not \_SB.PCI0, otherwise it raises a yellow bang in the Device Manager with an error indicating that the device could not find enough free resources (despite avoiding the proper SBREG BAR reservation in MCHC resources). TEST=Boot Windows 11 on MSI PRO Z790-P and notice the yellow bang near GPIO device in Device Manager is gone. Change-Id: I1e6259817eeb7bca833ed54834660544c819dc25 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/elkhartlake/gpio.c M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/jasperlake/gpio.c M src/soc/intel/meteorlake/acpi/gpio.asl M src/soc/intel/meteorlake/gpio.c M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_pch_h.asl M src/soc/intel/tigerlake/gpio.c M src/soc/intel/tigerlake/gpio_pch_h.c 19 files changed, 734 insertions(+), 710 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/77582/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/77582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6259817eeb7bca833ed54834660544c819dc25 Gerrit-Change-Number: 77582 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[master]: soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Tim Crawford, Werner Zeh. Hello Eran Mitrani, Jakub Czapiga, Jeremy Soller, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Tim Crawford, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77582?usp=email to look at the new patch set (#2). Change subject: soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB ...................................................................... soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB Windows expects the GPIO device to be under \_SB, not \_SB.PCI0, otherwise it raises a yellow bang in the Device Manager with an error indicating that the device could not find enough free resources (despite avoiding the proper SBREG BAR reservation in MCHC resources). TEST=Boot Windows 11 on MSI PRO Z790-P and notice the yellow bang near GPIO device in Device Manager is gone. Change-Id: I1e6259817eeb7bca833ed54834660544c819dc25 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/elkhartlake/gpio.c M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/jasperlake/gpio.c M src/soc/intel/meteorlake/acpi/gpio.asl M src/soc/intel/meteorlake/gpio.c M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_pch_h.asl M src/soc/intel/tigerlake/gpio.c M src/soc/intel/tigerlake/gpio_pch_h.c 19 files changed, 734 insertions(+), 710 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/77582/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6259817eeb7bca833ed54834660544c819dc25 Gerrit-Change-Number: 77582 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[master]: soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jonathon Hall, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77582?usp=email ) Change subject: soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB ...................................................................... soc/intel/gpio: Change the GPIO device scope in ACPI to \_SB Windows expects the GPIO device to be under \_SB, not \_SB.PCI0, otherwise it raises a yellow bang and an error indicating that the device could not find enough free resources (despite avoiding the SBREG BAR reservation in MCHC resources). TEST=Boot Windows 11 on MSI PRO Z790-P and notice the yellow bang near GPIO device in Device Manager is gone. Change-Id: I1e6259817eeb7bca833ed54834660544c819dc25 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/gpio_cnp_h.c M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/elkhartlake/gpio.c M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/jasperlake/gpio.c M src/soc/intel/meteorlake/acpi/gpio.asl M src/soc/intel/meteorlake/gpio.c M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_pch_h.asl M src/soc/intel/tigerlake/gpio.c M src/soc/intel/tigerlake/gpio_pch_h.c 19 files changed, 734 insertions(+), 710 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/77582/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl index ea7be7d..06d40ea 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl @@ -30,7 +30,7 @@ 0, // Debounce timeout 0, // Drive strength IoRestrictionOutputOnly, // Only used as output - "\\_SB.PCI0.GPIO", // GPIO controller + "\\_SB.GPIO", // GPIO controller 0) // Must be 0 { 296, // GPP_E8 - STATUSLED# diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index b57e41a..16fb305 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -5,125 +5,128 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) - Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM3) #endif - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) - /* GPIO Community 3 */ - CreateDWordField (^RBUF, ^COM3._BAS, BAS3) - CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - BAS3 = ^^PCRB (PID_GPIOCOM3) - LEN3 = GPIO_BASE_SIZE + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCI0.PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE #endif - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCI0.PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE - Return (RBUF) - } + Return (RBUF) + } - Name (SBRT, ResourceTemplate() - { - /* PCH_RESERVED/SBREG BAR resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Name (SBRT, ResourceTemplate() + { + /* PCH_RESERVED/SBREG BAR resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - /* Starting with the last community which have the lowest PID */ + /* Starting with the last community which have the lowest PID */ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) - MIN1 = P2SB_BAR + MIN1 = P2SB_BAR #else - MIN1 = PCH_PRESERVED_BASE_ADDRESS + MIN1 = PCH_PRESERVED_BASE_ADDRESS #endif - MAX1 = ^^PCRB (PID_GPIOCOM5) - 1 - LEN1 = MAX1 - MIN1 + 1 + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM5) - 1 + LEN1 = MAX1 - MIN1 + 1 - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) - MIN2 = ^^PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE #else - MIN2 = ^^PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE #endif - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) - MAX3 = P2SB_BAR + P2SB_SIZE - 1 + MAX3 = P2SB_BAR + P2SB_SIZE - 1 #else - MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 #endif - LEN3 = MAX3 - MIN3 + 1 + LEN3 = MAX3 - MIN3 + 1 - Return (SBRT) - } + Return (SBRT) + } - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 38774b1..db4564b 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -115,7 +115,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_BTA", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community0_groups, @@ -146,7 +146,7 @@ #else .name = "GPP_SDH", #endif - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community1_groups, @@ -171,7 +171,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpd, .num_reset_vals = ARRAY_SIZE(rst_map_gpd), .groups = adl_community2_groups, @@ -193,7 +193,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_VGPIO", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community3_groups, @@ -216,7 +216,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_FCE", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community4_groups, @@ -242,7 +242,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_RSPI0", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community5_groups, diff --git a/src/soc/intel/alderlake/gpio_pch_s.c b/src/soc/intel/alderlake/gpio_pch_s.c index d49daeb..3a54739 100644 --- a/src/soc/intel/alderlake/gpio_pch_s.c +++ b/src/soc/intel/alderlake/gpio_pch_s.c @@ -111,7 +111,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_IRJ", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community0_groups, @@ -135,7 +135,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_BGH", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community1_groups, @@ -158,7 +158,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpd, .num_reset_vals = ARRAY_SIZE(rst_map_gpd), .groups = adl_community2_groups, @@ -178,7 +178,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_AC", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community3_groups, @@ -202,7 +202,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_SEKF", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community4_groups, @@ -226,7 +226,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_D", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), .groups = adl_community5_groups, diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index adf6825..cba9ff8 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -4,101 +4,104 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, "INT34BB") - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) + Name (_HID, "INT34BB") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - /* - * GPIO communities 0, 1, and 4 are exported for the OS. - * This is based on the Linux kernel provided community map at - * drivers/pinctrl/intel/pinctrl-cannonlake.c:cnllp_communities[] - */ - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + /* + * GPIO communities 0, 1, and 4 are exported for the OS. + * This is based on the Linux kernel provided community map at + * drivers/pinctrl/intel/pinctrl-cannonlake.c:cnllp_communities[] + */ + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* PCH reserved resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + Name (SBRT, ResourceTemplate() + { + /* PCH reserved resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = PCH_PRESERVED_BASE_ADDRESS - MAX1 = ^^PCRB (PID_GPIOCOM4) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = PCH_PRESERVED_BASE_ADDRESS + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM4) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 - LEN3 = MAX3 - MIN3 + 1 + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - Return (SBRT) - } + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + LEN3 = MAX3 - MIN3 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index 7031b6a..4baa2b2 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -4,108 +4,111 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, "INT3450") - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM3) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) + Name (_HID, "INT3450") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - /* - * GPIO communities 0, 1, 3, and 4 are exported for the OS. - * This is based on the Linux kernel provided community map at - * drivers/pinctrl/intel/pinctrl-cannonlake.c:cnhl_communities[] - */ - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + /* + * GPIO communities 0, 1, 3, and 4 are exported for the OS. + * This is based on the Linux kernel provided community map at + * drivers/pinctrl/intel/pinctrl-cannonlake.c:cnhl_communities[] + */ + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 3 */ - CreateDWordField (^RBUF, ^COM3._BAS, BAS3) - CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - BAS3 = ^^PCRB (PID_GPIOCOM3) - LEN3 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCI0.PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* PCH reserved resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + Name (SBRT, ResourceTemplate() + { + /* PCH reserved resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = PCH_PRESERVED_BASE_ADDRESS - MAX1 = ^^PCRB (PID_GPIOCOM4) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = PCH_PRESERVED_BASE_ADDRESS + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM4) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 - LEN3 = MAX3 - MIN3 + 1 + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - Return (SBRT) - } + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + LEN3 = MAX3 - MIN3 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 93a71e0..3d3c9e7 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -82,7 +82,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_ABG", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = cnl_community0_groups, @@ -106,7 +106,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_DFH", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, @@ -130,7 +130,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community2_groups, @@ -154,7 +154,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GP_AC", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, @@ -178,7 +178,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CEJ", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community4_groups, diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c index 4189ebf..8a5e04f 100644 --- a/src/soc/intel/cannonlake/gpio_cnp_h.c +++ b/src/soc/intel/cannonlake/gpio_cnp_h.c @@ -82,7 +82,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_AB", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community0_groups, @@ -104,7 +104,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CDG", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community1_groups, @@ -126,7 +126,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpd, .num_reset_vals = ARRAY_SIZE(rst_map_gpd), .groups = cnl_community2_groups, @@ -148,7 +148,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_KHEF", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community3_groups, @@ -170,7 +170,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_IJ", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = cnl_community4_groups, diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index f352f4e9..aba4862 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -210,7 +210,7 @@ } /* Concatenate the SBREG BAR or PCH_RESERVED resource with GPIO holes */ - ConcatenateResTemplate (MCRS, \_SB.PCI0.GPIO.SBRS(), Local0) + ConcatenateResTemplate (MCRS, \_SB.GPIO.SBRS(), Local0) Return (Local0) } diff --git a/src/soc/intel/elkhartlake/acpi/gpio.asl b/src/soc/intel/elkhartlake/acpi/gpio.asl index f89fa17..4626b64 100644 --- a/src/soc/intel/elkhartlake/acpi/gpio.asl +++ b/src/soc/intel/elkhartlake/acpi/gpio.asl @@ -6,104 +6,107 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM2) - Memory32Fixed (ReadWrite, 0, 0, COM3) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 2 */ - CreateDWordField (^RBUF, ^COM2._BAS, BAS2) - CreateDWordField (^RBUF, ^COM2._LEN, LEN2) - BAS2 = ^^PCRB (PID_GPIOCOM2) - LEN2 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE - /* GPIO Community 3 */ - CreateDWordField (^RBUF, ^COM3._BAS, BAS3) - CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - BAS3 = ^^PCRB (PID_GPIOCOM3) - LEN3 = GPIO_BASE_SIZE + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCI0.PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCI0.PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCI0.PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* PCH reserved resource split into 2 with GPIO hole */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) - }) + Name (SBRT, ResourceTemplate() + { + /* PCH reserved resource split into 2 with GPIO hole */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = PCH_PRESERVED_BASE_ADDRESS - MAX1 = ^^PCRB (PID_GPIOCOM5) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = PCH_PRESERVED_BASE_ADDRESS + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM5) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX2 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - Return (SBRT) - } + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX2 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + LEN2 = MAX2 - MIN2 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } /* diff --git a/src/soc/intel/elkhartlake/gpio.c b/src/soc/intel/elkhartlake/gpio.c index 1b07bc5..dcd93a0 100644 --- a/src/soc/intel/elkhartlake/gpio.c +++ b/src/soc/intel/elkhartlake/gpio.c @@ -87,7 +87,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_BTG", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = ehl_community0_groups, @@ -109,7 +109,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_VHDU", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = ehl_community1_groups, @@ -129,7 +129,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_gpd, .num_reset_vals = ARRAY_SIZE(rst_map_gpd), .groups = ehl_community2_groups, @@ -151,7 +151,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_SA", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = ehl_community3_groups, @@ -173,7 +173,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CFE", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = ehl_community4_groups, @@ -195,7 +195,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_RR", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = ehl_community5_groups, diff --git a/src/soc/intel/jasperlake/acpi/gpio.asl b/src/soc/intel/jasperlake/acpi/gpio.asl index 012cbfa..3a48126 100644 --- a/src/soc/intel/jasperlake/acpi/gpio.asl +++ b/src/soc/intel/jasperlake/acpi/gpio.asl @@ -7,103 +7,106 @@ #include <soc/intel/common/acpi/gpio.asl> -Device (GPIO) +Scope (\_SB) { - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCI0.PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* PCH reserved resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + Name (SBRT, ResourceTemplate() + { + /* PCH reserved resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = PCH_PRESERVED_BASE_ADDRESS - MAX1 = ^^PCRB (PID_GPIOCOM5) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = PCH_PRESERVED_BASE_ADDRESS + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM5) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 - LEN3 = MAX3 - MIN3 + 1 + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - Return (SBRT) - } + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + LEN3 = MAX3 - MIN3 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } /* diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 42eb183..c8c4c4a 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -80,7 +80,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_FBASR", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_com0, .num_reset_vals = ARRAY_SIZE(rst_map_com0), .groups = jsl_community0_groups, @@ -102,7 +102,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_HDC", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = jsl_community1_groups, @@ -122,7 +122,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = jsl_community2_groups, @@ -144,7 +144,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_E", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = jsl_community4_groups, @@ -166,7 +166,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_G", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = jsl_community5_groups, diff --git a/src/soc/intel/meteorlake/acpi/gpio.asl b/src/soc/intel/meteorlake/acpi/gpio.asl index 39eec05..1e8303c 100644 --- a/src/soc/intel/meteorlake/acpi/gpio.asl +++ b/src/soc/intel/meteorlake/acpi/gpio.asl @@ -5,109 +5,112 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, CROS_GPIO_NAME) - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM3) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 3 */ - CreateDWordField (^RBUF, ^COM3._BAS, BAS3) - CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - BAS3 = ^^PCRB (PID_GPIOCOM3) - LEN3 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_BmGetNextLoadOptionBufferGPIOCOM1) + LEN1 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCI0.PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCI0.PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* SBREG BAR reserved resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + Name (SBRT, ResourceTemplate() + { + /* SBREG BAR reserved resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = P2SB_BAR - MAX1 = ^^PCRB (PID_GPIOCOM5) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = P2SB_BAR + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM5) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX3 = P2SB_BAR + P2SB_SIZE - 1 - LEN3 = MAX3 - MIN3 + 1 + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - Return (SBRT) - } + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX3 = P2SB_BAR + P2SB_SIZE - 1 + LEN3 = MAX3 - MIN3 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } diff --git a/src/soc/intel/meteorlake/gpio.c b/src/soc/intel/meteorlake/gpio.c index d4cbe0c..cbbc663 100644 --- a/src/soc/intel/meteorlake/gpio.c +++ b/src/soc/intel/meteorlake/gpio.c @@ -92,7 +92,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CPUVC", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = mtl_community0_groups, @@ -120,7 +120,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_AE", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = mtl_community1_groups, @@ -144,7 +144,7 @@ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_HFSPI0VG3", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = mtl_community3_groups, @@ -168,7 +168,7 @@ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_SJTAG", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = mtl_community4_groups, @@ -193,7 +193,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_BDVG", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = mtl_community5_groups, diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl index e575eb9..b285632 100644 --- a/src/soc/intel/tigerlake/acpi/gpio.asl +++ b/src/soc/intel/tigerlake/acpi/gpio.asl @@ -5,102 +5,105 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, "INT34C5") - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (_HID, "INT34C5") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCI0.PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* PCH reserved resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + Name (SBRT, ResourceTemplate() + { + /* PCH reserved resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = PCH_PRESERVED_BASE_ADDRESS - MAX1 = ^^PCRB (PID_GPIOCOM5) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = PCH_PRESERVED_BASE_ADDRESS + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM5) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM4) + GPIO_BASE_SIZE + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 - LEN3 = MAX3 - MIN3 + 1 + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - Return (SBRT) - } + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + LEN3 = MAX3 - MIN3 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } diff --git a/src/soc/intel/tigerlake/acpi/gpio_pch_h.asl b/src/soc/intel/tigerlake/acpi/gpio_pch_h.asl index 107b700..6b30c2b 100644 --- a/src/soc/intel/tigerlake/acpi/gpio_pch_h.asl +++ b/src/soc/intel/tigerlake/acpi/gpio_pch_h.asl @@ -7,109 +7,112 @@ #include <soc/irq.h> #include <soc/pcr_ids.h> -Device (GPIO) +Scope (\_SB) { - Name (_HID, "INT34C6") - Name (_UID, 0) - Name (_DDN, "GPIO Controller") - - Name (RBUF, ResourceTemplate() + Device (GPIO) { - Memory32Fixed (ReadWrite, 0, 0, COM0) - Memory32Fixed (ReadWrite, 0, 0, COM1) - Memory32Fixed (ReadWrite, 0, 0, COM3) - Memory32Fixed (ReadWrite, 0, 0, COM4) - Memory32Fixed (ReadWrite, 0, 0, COM5) - Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) - { GPIO_IRQ14 } - }) - Method (_CRS, 0, NotSerialized) - { - /* GPIO Community 0 */ - CreateDWordField (^RBUF, ^COM0._BAS, BAS0) - CreateDWordField (^RBUF, ^COM0._LEN, LEN0) - BAS0 = ^^PCRB (PID_GPIOCOM0) - LEN0 = GPIO_BASE_SIZE + Name (_HID, "INT34C6") + Name (_UID, 0) + Name (_DDN, "GPIO Controller") - /* GPIO Community 1 */ - CreateDWordField (^RBUF, ^COM1._BAS, BAS1) - CreateDWordField (^RBUF, ^COM1._LEN, LEN1) - BAS1 = ^^PCRB (PID_GPIOCOM1) - LEN1 = GPIO_BASE_SIZE + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCI0.PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE - /* GPIO Community 3 */ - CreateDWordField (^RBUF, ^COM3._BAS, BAS3) - CreateDWordField (^RBUF, ^COM3._LEN, LEN3) - BAS3 = ^^PCRB (PID_GPIOCOM3) - LEN3 = GPIO_BASE_SIZE + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCI0.PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE - /* GPIO Community 4 */ - CreateDWordField (^RBUF, ^COM4._BAS, BAS4) - CreateDWordField (^RBUF, ^COM4._LEN, LEN4) - BAS4 = ^^PCRB (PID_GPIOCOM4) - LEN4 = GPIO_BASE_SIZE + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCI0.PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE - /* GPIO Community 5 */ - CreateDWordField (^RBUF, ^COM5._BAS, BAS5) - CreateDWordField (^RBUF, ^COM5._LEN, LEN5) - BAS5 = ^^PCRB (PID_GPIOCOM5) - LEN5 = GPIO_BASE_SIZE + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCI0.PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE - Return (RBUF) - } + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCI0.PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE - Name (SBRT, ResourceTemplate() - { - /* PCH reserved resource split into 3 with GPIO holes */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR1) + Return (RBUF) + } - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR2) + Name (SBRT, ResourceTemplate() + { + /* PCH reserved resource split into 3 with GPIO holes */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR1) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000,,, SBR3) - }) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR2) - Method (SBRS, 0, NotSerialized) - { - CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) - CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) - CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000,,, SBR3) + }) - /* Starting with the last community which have the lowest PID */ - MIN1 = PCH_PRESERVED_BASE_ADDRESS - MAX1 = ^^PCRB (PID_GPIOCOM5) - 1 - LEN1 = MAX1 - MIN1 + 1 + Method (SBRS, 0, NotSerialized) + { + CreateDwordField (^SBRT, ^SBR1._MIN, MIN1) + CreateDwordField (^SBRT, ^SBR1._MAX, MAX1) + CreateDwordField (^SBRT, ^SBR1._LEN, LEN1) - CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) - CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) - CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) + /* Starting with the last community which have the lowest PID */ + MIN1 = PCH_PRESERVED_BASE_ADDRESS + MAX1 = ^^PCI0.PCRB (PID_GPIOCOM5) - 1 + LEN1 = MAX1 - MIN1 + 1 - MIN2 = ^^PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE - MAX2 = ^^PCRB (PID_GPIOCOM1) - 1 - LEN2 = MAX2 - MIN2 + 1 + CreateDwordField (^SBRT, ^SBR2._MIN, MIN2) + CreateDwordField (^SBRT, ^SBR2._MAX, MAX2) + CreateDwordField (^SBRT, ^SBR2._LEN, LEN2) - CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) - CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) - CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) + MIN2 = ^^PCI0.PCRB (PID_GPIOCOM3) + GPIO_BASE_SIZE + MAX2 = ^^PCI0.PCRB (PID_GPIOCOM1) - 1 + LEN2 = MAX2 - MIN2 + 1 - MIN3 = ^^PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE - MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 - LEN3 = MAX3 - MIN3 + 1 + CreateDwordField (^SBRT, ^SBR3._MIN, MIN3) + CreateDwordField (^SBRT, ^SBR3._MAX, MAX3) + CreateDwordField (^SBRT, ^SBR3._LEN, LEN3) - Return (SBRT) - } + MIN3 = ^^PCI0.PCRB (PID_GPIOCOM0) + GPIO_BASE_SIZE + MAX3 = PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE - 1 + LEN3 = MAX3 - MIN3 + 1 - Method (_STA, 0, NotSerialized) - { - Return (0xF) + Return (SBRT) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } } } diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c index 7053f3a..6c9eaed 100644 --- a/src/soc/intel/tigerlake/gpio.c +++ b/src/soc/intel/tigerlake/gpio.c @@ -105,7 +105,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_BTA", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community0_groups, @@ -132,7 +132,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_SDHU", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community1_groups, @@ -158,7 +158,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_com2, .num_reset_vals = ARRAY_SIZE(rst_map_com2), .groups = tgl_community2_groups, @@ -182,7 +182,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_FCE", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community4_groups, @@ -209,7 +209,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CPU_VBPIO", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community5_groups, diff --git a/src/soc/intel/tigerlake/gpio_pch_h.c b/src/soc/intel/tigerlake/gpio_pch_h.c index 64662d7..d77499e 100644 --- a/src/soc/intel/tigerlake/gpio_pch_h.c +++ b/src/soc/intel/tigerlake/gpio_pch_h.c @@ -88,7 +88,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_ARB", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community0_groups, @@ -109,7 +109,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_DCSG", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community1_groups, @@ -128,7 +128,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map_com2, .num_reset_vals = ARRAY_SIZE(rst_map_com2), .groups = tgl_community2_groups, @@ -149,7 +149,7 @@ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_EF", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community3_groups, @@ -168,7 +168,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_HJK", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community4_groups, @@ -187,7 +187,7 @@ .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_I", - .acpi_path = "\\_SB.PCI0.GPIO", + .acpi_path = "\\_SB.GPIO", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), .groups = tgl_community5_groups, -- To view, visit https://review.coreboot.org/c/coreboot/+/77582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6259817eeb7bca833ed54834660544c819dc25 Gerrit-Change-Number: 77582 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh. Hello Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#11). Change subject: intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly ...................................................................... intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Special treatment is required if the GPIO ACPI device is exposed and the GPIO driver claims a part of the SBREG BAR (or PCH_PRESERVED range depending on SBREG BAR placement). In such a case the SBREG BAR or PCH_PRESERVED resource has to be fragmented into pieces, which are not claimed by the GPIO driver. coreboot always exposes the GPIO device (_STA is hardcoded to 0xF). Add ACPI methods in SoC-specific gpio.asl files, which return the ResourceTemplate(s) of SBREG BAR or PCH_PRESERVED resource fragments not claimed by the GPIO device. Concatenate it with the other resources reported by MCHC device. TEST=Boot Windows 11 on MSI PRO Z790-P and notice the yellow bang near GPIO device in Device Manager disappeared. When whole SBREG BAR was reserved, the error indicated that device could not find enough free resources. Also, the GPIO device must be placed under \_SB scope for the yellow bang to disappear. Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/meteorlake/acpi/gpio.asl M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_pch_h.asl 11 files changed, 402 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 11 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[master]: mb/google/rex/var/rex0: Add HDMI GPIOs to early GPIO list
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77521?usp=email ) Change subject: mb/google/rex/var/rex0: Add HDMI GPIOs to early GPIO list ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182405 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182403 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182402 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182401 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182400 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182399 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182398 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182397 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182395 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/182394 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182393 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182392 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182391 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182390 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182389 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/77521?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13691850d09a442d5d5493a2b1dcf1145cf9797a Gerrit-Change-Number: 77521 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 10:34:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex: Enable Fast V-Mode for MTL-U 15W
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75763?usp=email ) Change subject: mb/google/rex: Enable Fast V-Mode for MTL-U 15W ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182388 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182386 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182385 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182384 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182383 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182382 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182381 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182380 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182378 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/182377 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182376 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182375 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182374 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182373 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182372 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05 Gerrit-Change-Number: 75763 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Erin Park <erin.park(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Sep 2023 10:20:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84
by Subrata Banik (Code Review) 01 Sep '23

01 Sep '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77561?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84 ...................................................................... vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84 Update header files for FSP for Meteor Lake platform from 3292.83 to 3323.84. The patch changess only a few spacing alignment for FSP-M header and added few PPR (Post Package Repair) related variable for MemInfoHob header. BUG=b:297965979 TEST=Able to build and boot google/rex. Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h 2 files changed, 10 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Ivy Jian: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index b69beba..1835b54 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1214,8 +1214,8 @@ UINT8 Avx2RatioOffset; /** Offset 0x0403 - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. + DEPRECATED. 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease + AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. **/ UINT8 Avx3RatioOffset; @@ -2793,7 +2793,7 @@ /** Offset 0x0C4A - Reserved **/ - UINT8 Reserved66[2]; + UINT8 Reserved66[2]; /** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No @@ -3016,8 +3016,8 @@ UINT8 Avx2VoltageScaleFactor; /** Offset 0x0DD8 - Avx512 Voltage Guardband Scaling Factor - AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 - in 1/100 units, where a value of 125 would apply a 1.25 scale factor. + DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range + is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx512VoltageScaleFactor; diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h index d28ed89..7660a30 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/MemInfoHob.h @@ -187,7 +187,7 @@ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. } MRC_CH_TIMING; @@ -203,7 +203,7 @@ UINT8 DimmId; UINT32 DimmCapacity; ///< DIMM size in MBytes. UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes UINT8 RankInDimm; ///< The number of ranks in this DIMM. UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. @@ -285,6 +285,9 @@ HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. BOOLEAN IsIbeccEnabled; UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status } MEMORY_INFO_DATA_HOB; /** -- To view, visit https://review.coreboot.org/c/coreboot/+/77561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56 Gerrit-Change-Number: 77561 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: mb/dell: Add OptiPlex 7020/9020 port
by Michael Büchler (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Angel Pons, Michał Żygowski, Máté Kukri, Stefan Reinauer. Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 25: Code-Review+1 (2 comments) Patchset: PS25: Thank you for your work on this port! I tested this on a 9020 mini tower (MT). See my comment on the PCI(e) slots. Except that, all seems to work, but I did not test extensively. It boots with both a Haswell and a Broadwell mrc.bin. I hope it's okay to give it a +1 as a non-regular contributor. File src/mainboard/dell/optiplex_9020/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55232/comment/5a231d7c_6001ad7d : PS25, Line 39: device pci 1c.1 off end : The mini tower (MT) variant has two additional slots compared to the UFF variant: * 1c.1: PCI (through a bridge chip: Texas Instruments XIO2001) * 1c.2: PCIe x1 I enabled the two marked devices for a local build and both slots then work. Maybe introduce variants with an overridetree.cb? -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 25 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:53:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Subrata Banik (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > > > MRC_WRITE_NV_LATE doesn't work. To summarize for SPR-SP, fsp_find_nv_storage_data() must be called after FSP-S has returned, because FSP_NON_VOLATILE_STORAGE_HOB is created in FSP-S. > > > > This is just violation of the spec where FSP-M should implement the FSP_NON_VOLATILE_STORAGE_HOB and not the FSP-S. > > As per FSP 2.4 specification , section 11.3 > > ``` > The bootloader needs to parse the HOB list to see if such a GUID HOB exists after > memory is initialized. The HOB shall be populated either after returning from > FSP Output FspMemoryInit() in API mode or after all notification call backs for > EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI are completed in dispatch mode > ``` > > > > > > Due to this Intel FSP problem, we need to keep ugly W/A in coreboot. > > > > now I have better picture, let me think and come back with yet another attempt I will bring this up with Intel FSP team during arch meetign. At this moment it sounded more W/A as implementation is not matching the spec -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:36:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Subrata Banik (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, Subrata Banik, TangYiwei, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > > MRC_WRITE_NV_LATE doesn't work. To summarize for SPR-SP, fsp_find_nv_storage_data() must be called after FSP-S has returned, because FSP_NON_VOLATILE_STORAGE_HOB is created in FSP-S. > > This is just violation of the spec where FSP-M should implement the FSP_NON_VOLATILE_STORAGE_HOB and not the FSP-S. As per FSP 2.4 specification , section 11.3 ``` The bootloader needs to parse the HOB list to see if such a GUID HOB exists after memory is initialized. The HOB shall be populated either after returning from FSP Output FspMemoryInit() in API mode or after all notification call backs for EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI are completed in dispatch mode ``` > > Due to this Intel FSP problem, we need to keep ugly W/A in coreboot. > > now I have better picture, let me think and come back with yet another attempt -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:35:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2023