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Change subject: mb/google/rex/var/karis: Drop unused audio codecs and amplifiers
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Change subject: mb/google/rex/var/karis: Drop unused audio codecs and amplifiers
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/rex/variants/karis/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/77602/comment/b835ad08_9f328fa2 :
PS2, Line 550: end
> device ref hda on end
Done, thanks!
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Change subject: mb/google/rex/var/karis: Drop unused audio codecs and amplifiers
......................................................................
mb/google/rex/var/karis: Drop unused audio codecs and amplifiers
BUG=b:294155897, b:295112765
TEST=emerge-rex coreboot
Change-Id: Ic7e272a484ea76dfc3a314b3597cbc18c856a9ca
Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/karis/overridetree.cb
2 files changed, 1 insertion(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/77602/3
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Change subject: mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/rex/var/karis: Drop unused audio codecs and amplifiers
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/rex/variants/karis/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/77602/comment/f9a5876a_beb24613 :
PS2, Line 550: end
device ref hda on end
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Change subject: mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
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Change subject: mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
......................................................................
mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/77603/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
index 430e67e..af9e25d 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <cf9_reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@@ -17,4 +18,9 @@
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
}
}
+
+ /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1
+ and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is
+ then used on the mainboard to generate the right reset timing. */
+ outb(FULL_RST, RST_CNT);
}
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Change subject: crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
......................................................................
crossgcc: Upgrade GCC from 11.4.0 to 13.2.0
Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
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D util/crossgcc/patches/gcc-11.4.0_gnat.patch
D util/crossgcc/patches/gcc-11.4.0_rv32iafc.patch
R util/crossgcc/patches/gcc-13.2.0_asan_shadow_offset_callback.patch
A util/crossgcc/patches/gcc-13.2.0_gnat.patch
R util/crossgcc/patches/gcc-13.2.0_libcpp.patch
R util/crossgcc/patches/gcc-13.2.0_libgcc.patch
D util/crossgcc/sum/gcc-11.4.0.tar.xz.cksum
A util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum
10 files changed, 116 insertions(+), 224 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/70771/24
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