coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Johnny Lin (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, Subrata Banik, TangYiwei, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > > MRC_WRITE_NV_LATE doesn't work. […] IIRC moving to fsp-s is because it has faster booting speed for server platform. -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:27:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh. Hello Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#10). Change subject: intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly ...................................................................... intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Special treatment is required if the GPIO ACPI device is exposed and the GPIO driver claims a part of the SBREG BAR (or PCH_PRESERVED range depending on SBREG BAR placement). In such a case the SBREG BAR or PCH_PRESERVED resource has to be fragmented into pieces, which are not claimed by the GPIO driver. coreboot always exposes the GPIO device (_STA is hardcoded to 0xF). Add ACPI methods in SoC-specific gpio.asl files, which return the ResourceTemplate(s) of SBREG BAR or PCH_PRESERVED resource fragments not claimed by the GPIO device. Concatenate it with the other resources reported by MCHC device. TEST=Boot Windows 11 on MSI PRO Z790-P and notice the yellow bang near GPIO device in Device Manager disappeared. When whole SBREG BAR was reserved, the error indicated that device could not find enough free resources. Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/meteorlake/acpi/gpio.asl M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_pch_h.asl 11 files changed, 402 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Subrata Banik (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > MRC_WRITE_NV_LATE doesn't work. To summarize for SPR-SP, fsp_find_nv_storage_data() must be called after FSP-S has returned, because FSP_NON_VOLATILE_STORAGE_HOB is created in FSP-S. This is just violation of the spec where FSP-M should implement the FSP_NON_VOLATILE_STORAGE_HOB and not the FSP-S. Due to this Intel FSP problem, we need to keep ugly W/A in coreboot. now I have better picture, let me think and come back with yet another attempt -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:05:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Johnny Lin (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > I pick all 4 cls: […] MRC_WRITE_NV_LATE doesn't work. To summarize for SPR-SP, fsp_find_nv_storage_data() must be called after FSP-S has returned, because FSP_NON_VOLATILE_STORAGE_HOB is created in FSP-S. -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:02:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Subrata Banik (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > I pick all 4 cls: > 77594/2, 77557/3, 77556/5, 77295/11 but doesn't work. because CB:77556 save_memory_training_data() is only being run after FSP-M and not after FSP-S, for our case there is no FSP_NON_VOLATILE_STORAGE_HOB can be stashed. > at romstage: > [SPEW ] Calling FspMemoryInit: 0xff058f30 > .. > [ERROR] FSP_NON_VOLATILE_STORAGE_HOB missing! > [SPEW ] FspMemoryInit returned 0x00000000 can you tell me at which stage in ur platform, FSP provides FSP_NON_VOLATILE_STORAGE_HOB ? romstage or ramstage (aka FSP-S)? > > at ramstage: > [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1367 / 5984 ms > [DEBUG] FMAP: area RW_MRC_CACHE found @ 3000000 (65536 bytes) > [INFO ] MRC: No data in cbmem for 'RW_MRC_CACHE'. > > Do I need to select MRC_WRITE_NV_LATE or anything? This is internally set MRC_STASH_TO_CBMEM config so no difference. -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 09:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG
by Chen Wisley (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Nick Vaccaro, Subrata Banik, Wisley Chen. Hello Nick Vaccaro, Subrata Banik, Wisley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77604?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG ...................................................................... mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG Configure the AUX pins as NC based on the FW_CONFIG setting when the C1 port is not present. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yaviks/fw_config.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/77604/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/77604?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Gerrit-Change-Number: 77604 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Johnny Lin (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Kapil Porwal, Lean Sheng Tan, Nill Ge, Reka Norman, Shuo Liu, Subrata Banik, TangYiwei, Tim Chu. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > > I based on the same upstream tip and pick your latest 2 changes: […] I pick all 4 cls: 77594/2, 77557/3, 77556/5, 77295/11 but doesn't work. because CB:77556 save_memory_training_data() is only being run after FSP-M and not after FSP-S, for our case there is no FSP_NON_VOLATILE_STORAGE_HOB can be stashed. at romstage: [SPEW ] Calling FspMemoryInit: 0xff058f30 .. [ERROR] FSP_NON_VOLATILE_STORAGE_HOB missing! [SPEW ] FspMemoryInit returned 0x00000000 at ramstage: [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1367 / 5984 ms [DEBUG] FMAP: area RW_MRC_CACHE found @ 3000000 (65536 bytes) [INFO ] MRC: No data in cbmem for 'RW_MRC_CACHE'. Do I need to select MRC_WRITE_NV_LATE or anything? -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 08:48:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: sb/amd/hudson: Skip setting up LPC decode for base < 0x20
by Arthur Heymans (Code Review) 01 Sep '23

01 Sep '23

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54669?usp=email ) Change subject: sb/amd/hudson: Skip setting up LPC decode for base < 0x20 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Which Super I/O chip driver really checks allowed boundaries specified in its datasheet? None. Each mainboard's devictree is created with an assumption that unassigned io/irq resource is just disabled resource. > 1. The Super I/O drivers should start checking the resources in terms of boundaries (and maybe resource existence, i.e. whether devicetree sets it) > 2. The PNP driver which assigns resources should also understand that zero resources are disabled resources if we don't do it in the point 1. I had https://review.coreboot.org/c/coreboot/+/54686 implemented as a more generic solution. -- To view, visit https://review.coreboot.org/c/coreboot/+/54669?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idec3832d8d1ab95ae9747ce87792ee7b474540c7 Gerrit-Change-Number: 54669 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 01 Sep 2023 08:37:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG
by Chen Wisley (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Nick Vaccaro, Subrata Banik. Hello Nick Vaccaro, Subrata Banik, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77604?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG ...................................................................... mb/google/nissa/var/yaviks: Disable AUX pins based on FW_CONFIG Configure the AUX pins as NC based on the FW_CONFIG setting when the C1 port is not present. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/yaviks/fw_config.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/77604/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77604?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24fb8f16c2e3b05edf1056b5687ae5ea28c022c0 Gerrit-Change-Number: 77604 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen%quantatw.com(a)gtempaccount.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly
by Michał Żygowski (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh. Hello Eran Mitrani, Jakub Czapiga, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Subrata Banik, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77445?usp=email to look at the new patch set (#9). Change subject: intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly ...................................................................... intelblocks/acpi: Reserve SBREG BAR/PCH_PRESERVED resource properly Reserve SBREG BAR if it is outside of the PCH reserved memory range. Desktop series processors have larger SBREG BARs, which, unlike mobile processors, do not fall into the standard PCH reserved range (0xfc800000 - 0xfe7fffff). Special treatment is required if the GPIO ACPI device is exposed and the GPIO driver claims a part of the SBREG BAR (or PCH_PRESERVED range depending on SBREG BAR placement). In such a case the SBREG BAR or PCH_PRESERVED resource has to be fragmented into pieces, which are not claimed by the GPIO driver. coreboot always exposes the GPIO device (_STA is hardcoded to 0xF). Add ACPI methods in SoC-specific gpio.asl files, which return the ResourceTemplate(s) of SBREG BAR or PCH_PRESERVED resource fragments not claimed by the GPIO device. Concatenate it with the other resources reported by MCHC device. Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/include/soc/iomap.h M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl M src/soc/intel/common/block/acpi/acpi/northbridge.asl M src/soc/intel/elkhartlake/acpi/gpio.asl M src/soc/intel/jasperlake/acpi/gpio.asl M src/soc/intel/meteorlake/acpi/gpio.asl M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/tigerlake/acpi/gpio.asl M src/soc/intel/tigerlake/acpi/gpio_pch_h.asl 11 files changed, 402 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/77445/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/77445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaf45daba37e3acfcea0e653df69fa5c2f480c4a Gerrit-Change-Number: 77445 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2023