coreboot-gerrit September 2023

coreboot-gerrit@coreboot.org

1 participants
3824 discussions

[XS] Change in coreboot[master]: MAINTAINERS: Remove rrangel from amd common
by Raul Rangel (Code Review) 01 Sep '23

01 Sep '23

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77609?usp=email ) Change subject: MAINTAINERS: Remove rrangel from amd common ...................................................................... MAINTAINERS: Remove rrangel from amd common The AMD team is large enough to handle it on their own :) Change-Id: I58bc265d9ecfdcb8904f32fbc917877211b7f658 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M MAINTAINERS 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/77609/1 diff --git a/MAINTAINERS b/MAINTAINERS index 64910d2..c3440e6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -810,7 +810,6 @@ AMD Cezanne M: Felix Held <felix-coreboot(a)felixheld.de> M: Jason Glenesk <jason.glenesk(a)gmail.com> -M: Raul E Rangel <rrangel(a)chromium.org> M: Fred Reitberger <reitbergerfred(a)gmail.com> M: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> L: amd_coreboot_org_changes(a)googlegroups.com @@ -821,7 +820,6 @@ AMD common SoC code M: Felix Held <felix-coreboot(a)felixheld.de> M: Jason Glenesk <jason.glenesk(a)gmail.com> -M: Raul E Rangel <rrangel(a)chromium.org> M: Fred Reitberger <reitbergerfred(a)gmail.com> M: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> L: amd_coreboot_org_changes(a)googlegroups.com @@ -841,7 +839,6 @@ AMD Mendocino M: Felix Held <felix-coreboot(a)felixheld.de> M: Jason Glenesk <jason.glenesk(a)gmail.com> -M: Raul E Rangel <rrangel(a)chromium.org> M: Fred Reitberger <reitbergerfred(a)gmail.com> M: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> L: amd_coreboot_org_changes(a)googlegroups.com -- To view, visit https://review.coreboot.org/c/coreboot/+/77609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58bc265d9ecfdcb8904f32fbc917877211b7f658 Gerrit-Change-Number: 77609 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/amd/common/data_fabric: add support for extended MMIO addresses
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77514?usp=email ) Change subject: soc/amd/common/data_fabric: add support for extended MMIO addresses ...................................................................... Patch Set 5: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182424 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182422 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182421 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182420 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182419 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182418 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182417 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182416 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182414 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/182413 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182412 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182411 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182410 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182409 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182408 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/77514?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic304f5797bc5661c1d511c95e457c6dde169d329 Gerrit-Change-Number: 77514 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 15:34:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex/var/karis: Update GPIO settings for NC pins
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77558?usp=email ) Change subject: mb/google/rex/var/karis: Update GPIO settings for NC pins ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182441 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182439 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182438 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182437 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182436 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182435 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182434 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182433 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/182432 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182431 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182429 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182428 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182427 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182426 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182425 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/77558?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1f847d2db83b63a351203f0449cc1368bef27f4 Gerrit-Change-Number: 77558 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 15:20:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: abuild:skyrim: Remove the setting for AMD FW base in configs
by 9elements QA (Code Review) 01 Sep '23

01 Sep '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77518?usp=email ) Change subject: abuild:skyrim: Remove the setting for AMD FW base in configs ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182458 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/182456 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/182455 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/182454 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/182453 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182452 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/182451 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/182450 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/182448 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/182447 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/182446 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/182445 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/182444 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/182443 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/182442 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/77518?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56e0501b511866b8ccc200b55620f87883e12067 Gerrit-Change-Number: 77518 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Sep 2023 15:06:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: device/device.h: Drop acpi_inject_dsdt
by Tim Wawrzynczak (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Felix Held, Felix Singer, Lance Zhao, Subrata Banik, Tarun Tuli. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70502?usp=email ) Change subject: device/device.h: Drop acpi_inject_dsdt ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/70502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e100cf650b3654240dbf19e1ee3069980fbe93 Gerrit-Change-Number: 70502 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 01 Sep 2023 14:56:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/mendocino: Specify and use FSP binaries for platform
by Matt DeVillier (Code Review) 01 Sep '23

01 Sep '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77625?usp=email ) Change subject: soc/amd/mendocino: Specify and use FSP binaries for platform ...................................................................... soc/amd/mendocino: Specify and use FSP binaries for platform Specify the default path to, and automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in previous patforms. TEST=build/boot google/skyrim Change-Id: Ic837d264327723c8dc18a60fb16e8d41fe38b44e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/amd/mendocino/Kconfig 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/77625/1 diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 189c6b9..98a2e55 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -3,6 +3,7 @@ config SOC_AMD_REMBRANDT_BASE bool select ACPI_SOC_NVS + select ADD_FSP_BINARIES if USE_AMD_BLOBS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select CACHE_MRC_SETTINGS @@ -111,6 +112,20 @@ default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO default "soc/amd/mendocino/chipset_rembrandt.cb" +config FSP_M_FILE + string "FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/mendocino/MENDOCINO_M.fd" if SOC_AMD_MENDOCINO + help + The path and filename of the FSP-M binary for this platform. + +config FSP_S_FILE + string "FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/mendocino/MENDOCINO_S.fd" if SOC_AMD_MENDOCINO + help + The path and filename of the FSP-S binary for this platform. + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/77625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic837d264327723c8dc18a60fb16e8d41fe38b44e Gerrit-Change-Number: 77625 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[master]: soc/amd/cezanne: select ADD_FSP_BINARIES if USE_AMD_BLOBS
by Matt DeVillier (Code Review) 01 Sep '23

01 Sep '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77624?usp=email ) Change subject: soc/amd/cezanne: select ADD_FSP_BINARIES if USE_AMD_BLOBS ...................................................................... soc/amd/cezanne: select ADD_FSP_BINARIES if USE_AMD_BLOBS Automatically include the FSP binaries needed to boot a board if USE_AMD_BLOBS is selected. Simplifies board configs, and matches use in soc/amd/picasso. TEST=build/boot google/guybrush Change-Id: I5b6e34085410a2aafe5d7876be5097f28f521ce8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/77624/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2c6e949..a38686a 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -3,6 +3,7 @@ config SOC_AMD_CEZANNE bool select ACPI_SOC_NVS + select ADD_FSP_BINARIES if USE_AMD_BLOBS select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/77624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e34085410a2aafe5d7876be5097f28f521ce8 Gerrit-Change-Number: 77624 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/rex/var/ovis: Add DPTF configuration
by Jakub Czapiga (Code Review) 01 Sep '23

01 Sep '23

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77623?usp=email ) Change subject: mb/google/rex/var/ovis: Add DPTF configuration ...................................................................... mb/google/rex/var/ovis: Add DPTF configuration BUG=b:286834207 TEST=Build and boot google/ovis and check ACPI SSDT for DPTF entries Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/77623/1 diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 17d75cb..e76edf4 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -53,6 +53,73 @@ device domain 0 on device ref dtt on chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + }, + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 28000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 120000, + .max_power = 120000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/77623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia40884b3abd1417dea6ad291de4845762ee01966 Gerrit-Change-Number: 77623 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: Documentation: Update coding_style.md with refactoring section
by Martin Roth (Code Review) 01 Sep '23

01 Sep '23

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71067?usp=email ) Change subject: Documentation: Update coding_style.md with refactoring section ...................................................................... Documentation: Update coding_style.md with refactoring section The rule being added to the refactoring section is already present in the "coding style" section of the guide, but is currently easy to miss. Adding it to its own section makes it a little more plain and makes it more strongly worded. Update a couple of other areas: - Make kernel specific phrasing better aligned with coreboot. - Remove duplicate "try to match" phrase in coding style section. - Remove section on Data structures - it doesn't apply to coreboot. - Update text to make it clearer and more coreboot-centric. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic3508529f639ea0609d2ea2032cc52407e9543e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71067 Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M Documentation/contributing/coding_style.md 1 file changed, 46 insertions(+), 75 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Elyes Haouas: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index 5b2919e3..bdf6c60 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -6,14 +6,14 @@ the [Linux kernel coding style](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/p… The guidelines in this file should be seen as a strong suggestion, and -should overrule personal preference. But they may be ignored in -individual instances when there are good practical reasons to do so, and -reviewers are in agreement. +should overrule personal preference. They may be ignored in individual +instances when there are good practical reasons to do so, and reviewers +are in agreement. Any style questions that are not mentioned in here should be decided between the author and reviewers on a case-by-case basis. When modifying existing files, authors should try to match the prevalent style in that -file -- otherwise, they should try to match similar existing files in +file -- otherwise, they should generally match similar existing files in coreboot. Bulk style changes to existing code ("cleanup patches") should avoid @@ -24,7 +24,8 @@ and neither is `clang-format`. These tools can be useful to find potential issues or simplify formatting in new submissions, but they were not designed to directly match this guide and may have false -positives. They should not be bulk-applied to change existing code.) +positives. They should not be bulk-applied to change existing code +except in cases where they directly match the style guide.) ## Indentation @@ -42,7 +43,8 @@ the code move too far to the right, and makes it hard to read on a 80-character terminal screen. The answer to that is that if you need more than 3 levels of indentation, you're screwed anyway, and should -fix your program. +fix your program. Note that coreboot has expanded the 80 character +limit to 96 characters to allow for modern wider screens. In short, 8-char indents make things easier to read, and have the added benefit of warning you when you're nesting your functions too deep. @@ -87,7 +89,9 @@ never used for indentation, and the above example is deliberately broken. -Get a decent editor and don't leave whitespace at the end of lines. +Get a decent editor and don't leave whitespace at the end of lines. This +will actually keep the patch from being tested in the CI, so patches +with ending whitespace cannot be merged. ## Breaking long lines and strings @@ -503,18 +507,14 @@ but try to avoid excess. Instead, put the comments at the head of the function, telling people what it does, and possibly WHY it does it. -When commenting the kernel API functions, please use the kernel-doc -format. See the files Documentation/kernel-doc-nano-HOWTO.txt and -scripts/kernel-doc for details. - -coreboot style for comments is the C89 "/* ... */" style. You may -use C99-style "// ..." comments. +coreboot style for comments is the C89 "/* ... */" style. You may also +use C99-style "// ..." comments for single-line comments. The preferred style for *short* (multi-line) comments is: ```c /* This is the preferred style for short multi-line - comments in the Linux kernel source code. + comments in the coreboot source code. Please use it consistently. */ ``` @@ -523,7 +523,7 @@ ```c /* * This is the preferred style for multi-line - * comments in the Linux kernel source code. + * comments in the coreboot source code. * Please use it consistently. * * Description: A column of asterisks on the left side, @@ -578,7 +578,8 @@ ``` This will make emacs go better with the kernel coding style for C files -below ~/src/linux-trees. +below ~/src/linux-trees. Obviously, this should be updated to match +your own paths for coreboot. But even if you fail in getting emacs to do sane formatting, not everything is lost: use "indent". @@ -626,38 +627,6 @@ For full documentation on the configuration files, see the file Documentation/kbuild/kconfig-language.txt. -Data structures ---------------- - -Data structures that have visibility outside the single-threaded -environment they are created and destroyed in should always have -reference counts. In the kernel, garbage collection doesn't exist (and -outside the kernel garbage collection is slow and inefficient), which -means that you absolutely _have_ to reference count all your uses. - -Reference counting means that you can avoid locking, and allows multiple -users to have access to the data structure in parallel - and not having -to worry about the structure suddenly going away from under them just -because they slept or did something else for a while. - -Note that locking is _not_ a replacement for reference counting. -Locking is used to keep data structures coherent, while reference -counting is a memory management technique. Usually both are needed, and -they are not to be confused with each other. - -Many data structures can indeed have two levels of reference counting, -when there are users of different "classes". The subclass count counts -the number of subclass users, and decrements the global count just once -when the subclass count goes to zero. - -Examples of this kind of "multi-level-reference-counting" can be found -in memory management ("struct mm_struct": mm_users and mm_count), -and in filesystem code ("struct super_block": s_count and -s_active). - -Remember: if another thread can find your data structure, and you don't -have a reference count on it, you almost certainly have a bug. - Macros, Enums and RTL --------------------- @@ -727,35 +696,19 @@ also covers RTL which is used frequently with assembly language in the kernel. -Printing kernel messages +Printing coreboot messages ------------------------ -Kernel developers like to be seen as literate. Do mind the spelling of -kernel messages to make a good impression. Do not use crippled words +coreboot developers like to be seen as literate. Do mind the spelling of +coreboot messages to make a good impression. Do not use crippled words like "dont"; use "do not" or "don't" instead. Make the messages concise, clear, and unambiguous. -Kernel messages do not have to be terminated with a period. +coreboot messages do not have to be terminated with a period. Printing numbers in parentheses (%d) adds no value and should be avoided. -There are a number of driver model diagnostic macros in -<linux/device.h> which you should use to make sure messages are -matched to the right device and driver, and are tagged with the right -level: dev_err(), dev_warn(), dev_info(), and so forth. For messages -that aren't associated with a particular device, <linux/printk.h> -defines pr_debug() and pr_info(). - -Coming up with good debugging messages can be quite a challenge; and -once you have them, they can be a huge help for remote troubleshooting. -Such messages should be compiled out when the DEBUG symbol is not -defined (that is, by default they are not included). When you use -dev_dbg() or pr_debug(), that's automatic. Many subsystems have -Kconfig options to turn on -DDEBUG. A related convention uses -VERBOSE_DEBUG to add dev_vdbg() messages to the ones already enabled -by DEBUG. - Allocating memory ----------------- @@ -792,12 +745,7 @@ There appears to be a common misperception that gcc has a magic "make me faster" speedup option called "inline". While the use of inlines can be appropriate (for example as a means of replacing macros, see -Chapter 12), it very often is not. Abundant use of the inline keyword -leads to a much bigger kernel, which in turn slows the system as a whole -down, due to a bigger icache footprint for the CPU and simply because -there is less memory available for the pagecache. Just think about it; a -pagecache miss causes a disk seek, which easily takes 5 milliseconds. -There are a LOT of cpu cycles that can go into these 5 milliseconds. +Chapter 12), it very often is not. A reasonable rule of thumb is to not put inline at functions that have more than 3 lines of code in them. An exception to this rule are the @@ -923,7 +871,7 @@ .c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks, including includes to other headers that don't follow that provision. Where a specific include order is required for technical reasons, it should be clearly -documented with comments. +documented with comments. This should not be the norm. Files should generally include every header they need a definition from directly (and not include any unnecessary extra headers). Excepted from @@ -1058,6 +1006,29 @@ should never rely on incidental GCC translation behavior that is not explicitly documented as a feature and could change at any moment. +Refactoring +----------- +Because refactoring existing code can add bugs to tested code, any +refactors should be done only with serious consideration. Refactoring +for style differences should only be done if the existing style +conflicts with a documented coreboot guideline. If you believe that the +style should be modified, the pros and cons can be discussed on the +mailing list and in the coreboot leadership meeting. + +Similarly, the original author should be respected. Changing working +code simply because of a stylistic disagreement is *prohibited*. This is +not saying that refactors that are objectively better (simpler, faster, +easier to understand) are not allowed, but there has to be a definite +improvement, not simply stylistic changes. + +Basically, when refactoring code, there should be a clear benefit to +the project and codebase. The reviewers and submitters get to make the +call on how to interpret this. + +When refactoring, adding unit tests to verify that the post-change +functionality matches or improves upon pre-change functionality is +encouraged. + References ---------- -- To view, visit https://review.coreboot.org/c/coreboot/+/71067?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3508529f639ea0609d2ea2032cc52407e9543e5 Gerrit-Change-Number: 71067 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: LinuxBoot: sync usage of LINUX_INITRAMFS_PATH
by Frans Hendriks (Code Review) 01 Sep '23

01 Sep '23

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77608?usp=email ) Change subject: LinuxBoot: sync usage of LINUX_INITRAMFS_PATH ...................................................................... LinuxBoot: sync usage of LINUX_INITRAMFS_PATH Building LinuxBoot with default options results in built error: build/initramfs_u-root.cpio.xz no such file or directory coreboot adds LINUXBOOT_INITRAMFS_PATH to ADDITIONAL_PAYLOAD_CONFIG and prebuilt-files. The default value is ´build/initramfs_u-root.cpio´ where coreboot expects a relative path to location. Update CONFIG_LINUXBOOT_INITRAMFS_PATH to contain absolute path to cpio file. Use this config in LinuxBoot/targets/u-root.mk to point to correct file location. BUG = N/A TEST = Built and boot facebook monolith Change-Id: If35cd2c2dc9307fc79311991162f7aeb1a15ae32 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/targets/u-root.mk 2 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/77608/1 diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 24bfe3f..c3773a9 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -131,7 +131,7 @@ config LINUXBOOT_INITRAMFS_PATH string "Path to initramfs" - default "build/initramfs_u-root.cpio" if LINUXBOOT_UROOT + default "$(top)/payloads/external/LinuxBoot/build/initramfs_u-root.cpio" if LINUXBOOT_UROOT if LINUXBOOT_BUILD_INITRAMFS diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index fff79df..0cc3b08 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -43,8 +43,7 @@ cd $(uroot_build); \ go build -o u-root . -#$(CONFIG_LINUXBOOT_INITRAMFS_PATH) -build/initramfs_u-root.cpio: $(uroot_build)/u-root +$(CONFIG_LINUXBOOT_INITRAMFS_PATH): $(uroot_build)/u-root GOARCH=$(UROOT_ARCH-y) $(uroot_build)/u-root \ -uroot-source $(uroot_build) \ - $(uroot_args) -o build/initramfs_u-root.cpio $(uroot_cmds) + $(uroot_args) -o $(CONFIG_LINUXBOOT_INITRAMFS_PATH) $(uroot_cmds) -- To view, visit https://review.coreboot.org/c/coreboot/+/77608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If35cd2c2dc9307fc79311991162f7aeb1a15ae32 Gerrit-Change-Number: 77608 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2023