coreboot-gerrit May 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Nick Vaccaro (Code Review) 02 May '23

02 May '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... soc/intel/alderlake: Disable C1E on RPL CPUs Since disabling C1E could improve acoustic noise for RPL, add judgement in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs . BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 7789cec..d5fa51a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -1011,6 +1011,11 @@ s_cfg->PkgCStateDemotion = 0; else s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; + + if (cpu_id == CPUID_RAPTORLAKE_P_J0 || cpu_id == CPUID_RAPTORLAKE_P_Q0) + s_cfg->C1e = 0; + else + s_cfg->C1e = 1; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 12 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: Kconfig: Group dependency on X86EMU_DEBUG
by Matt DeVillier (Code Review) 02 May '23

02 May '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74901 ) Change subject: Kconfig: Group dependency on X86EMU_DEBUG ...................................................................... Kconfig: Group dependency on X86EMU_DEBUG Change-Id: I6b53536a3d673350fa1b46891da2766b0bc149e8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74901 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig 1 file changed, 18 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 50381ae..f8d7f76 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1093,10 +1093,11 @@ If unsure, say N. +if X86EMU_DEBUG + config X86EMU_DEBUG_JMP bool "Trace JMP/RETF" default n - depends on X86EMU_DEBUG help Print information about JMP and RETF opcodes from x86emu. @@ -1107,7 +1108,6 @@ config X86EMU_DEBUG_TRACE bool "Trace all opcodes" default n - depends on X86EMU_DEBUG help Print _all_ opcodes that are executed by x86emu. @@ -1120,7 +1120,6 @@ config X86EMU_DEBUG_PNP bool "Log Plug&Play accesses" default n - depends on X86EMU_DEBUG help Print Plug And Play accesses made by option ROMs. @@ -1131,7 +1130,6 @@ config X86EMU_DEBUG_DISK bool "Log Disk I/O" default n - depends on X86EMU_DEBUG help Print Disk I/O related messages. @@ -1142,7 +1140,6 @@ config X86EMU_DEBUG_PMM bool "Log PMM" default n - depends on X86EMU_DEBUG help Print messages related to POST Memory Manager (PMM). @@ -1154,7 +1151,6 @@ config X86EMU_DEBUG_VBE bool "Debug VESA BIOS Extensions" default n - depends on X86EMU_DEBUG help Print messages related to VESA BIOS Extension (VBE) functions. @@ -1165,7 +1161,6 @@ config X86EMU_DEBUG_INT10 bool "Redirect INT10 output to console" default n - depends on X86EMU_DEBUG help Let INT10 (i.e. character output) calls print messages to debug output. @@ -1176,7 +1171,6 @@ config X86EMU_DEBUG_INTERRUPTS bool "Log intXX calls" default n - depends on X86EMU_DEBUG help Print messages related to interrupt handling. @@ -1187,7 +1181,6 @@ config X86EMU_DEBUG_CHECK_VMEM_ACCESS bool "Log special memory accesses" default n - depends on X86EMU_DEBUG help Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors) @@ -1199,7 +1192,6 @@ config X86EMU_DEBUG_MEM bool "Log all memory accesses" default n - depends on X86EMU_DEBUG help Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions. @@ -1211,7 +1203,6 @@ config X86EMU_DEBUG_IO bool "Log IO accesses" default n - depends on X86EMU_DEBUG help Print I/O accesses made by option ROM. @@ -1222,12 +1213,14 @@ config X86EMU_DEBUG_TIMINGS bool "Output timing information" default n - depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER + depends on HAVE_MONOTONIC_TIMER help Print timing information needed by i915tool. If unsure, say N. +endif + config DEBUG_SPI_FLASH bool "Output verbose SPI flash debug messages" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/74901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b53536a3d673350fa1b46891da2766b0bc149e8 Gerrit-Change-Number: 74901 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Jérémy Compostella (Code Review) 02 May '23

02 May '23

Attention is currently required from: Anil Kumar K, Subrata Banik, Paul Menzel, Himanshu Sahdev. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 29: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/c857c0cc_99f82b44 PS28, Line 14: #include <pc80/mc146818rtc.h> > this is required for cmos_write and cmos_read functions Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 29 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Comment-Date: Tue, 02 May 2023 18:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
by Jérémy Compostella (Code Review) 02 May '23

02 May '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74805 ) Change subject: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74805/comment/b59c4658_c959a977 PS3, Line 7: soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise > > soc/intel/cmn/cse: Do CSE sync by default in romstage […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 Gerrit-Change-Number: 74805 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 02 May 2023 18:22:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Add initial memory configuration
by Martin L Roth (Code Review) 02 May '23

02 May '23

Attention is currently required from: Martin Roth, Tim Van Patten, Karthik Ramasubramanian. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74745 ) Change subject: mb/google/myst: Add initial memory configuration ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/myst/variants/myst/memory/Makefile.inc: https://review.coreboot.org/c/coreboot/+/74745/comment/38902efa_e86356f5 PS1, Line 7: spd-2.hex I mean it's fine for the build, but why is the first (and only) spd called spd-2? Is something broken with the script? -- To view, visit https://review.coreboot.org/c/coreboot/+/74745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Gerrit-Change-Number: 74745 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 May 2023 18:22:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/entry16.S: Move reset vector to this file
by Martin L Roth (Code Review) 02 May '23

02 May '23

Attention is currently required from: Arthur Heymans. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74800 ) Change subject: cpu/x86/entry16.S: Move reset vector to this file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a4b7fe99875a1addf611f569990ff9a3beda3ba Gerrit-Change-Number: 74800 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 02 May 2023 18:20:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/reset16.S: Remove handcoded reset vector
by Martin L Roth (Code Review) 02 May '23

02 May '23

Attention is currently required from: Nico Huber, Subrata Banik, Dinesh Gehlot, Angel Pons, Julius Werner, Maximilian Brune, Arthur Heymans, Werner Zeh, ron minnich. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74797 ) Change subject: cpu/x86/reset16.S: Remove handcoded reset vector ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie371000c60d66c032a8dcccb98e7627df09d3aa4 Gerrit-Change-Number: 74797 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 02 May 2023 18:18:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 02 May '23

02 May '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Paul Menzel, Himanshu Sahdev. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 29: (4 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/5c2b456c_2e9a2393 PS27, Line 153: sizeof(struct psr_heci_fw_downgrade_backup_res) > `sizeof(*res)` is there any issue using sizeof with structure ? File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/4d4f3bb3_d7e53a91 PS28, Line 14: #include <pc80/mc146818rtc.h> > what is this needed for ? this is required for cmos_write and cmos_read functions https://review.coreboot.org/c/coreboot/+/74577/comment/510baa42_715e8585 PS28, Line 142: static enum cb_err cse_send_backup_psr_cmd(struct psr_heci_fw_downgrade_backup_res *res) > I don't think there is a lot of value having this as a dedicated function unless you have plan of us […] at the moment this function is only called during downgrade. i am not sure if this will be called in future from other code paths. so i used a dedicated function https://review.coreboot.org/c/coreboot/+/74577/comment/2f775e8b_1b1227ff PS28, Line 813: > coding style: I don't think there is any rule requiring a blank link at the beginning of a block. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 29 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Comment-Date: Tue, 02 May 2023 18:17:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Jérémy Compostella (Code Review) 02 May '23

02 May '23

Attention is currently required from: Anil Kumar K, Subrata Banik, Paul Menzel, Himanshu Sahdev. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 28: (5 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/504baa92_81a962bf PS27, Line 145: struct psr_heci_fw_downgrade_backup_req { : struct psr_heci_header header; : } __packed; Why do you need to define this ? https://review.coreboot.org/c/coreboot/+/74577/comment/49efbc5a_95267d3b PS27, Line 153: sizeof(struct psr_heci_fw_downgrade_backup_res) `sizeof(*res)` File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/d37d2c4d_9d7e5d50 PS28, Line 14: #include <pc80/mc146818rtc.h> what is this needed for ? https://review.coreboot.org/c/coreboot/+/74577/comment/869bc66a_009fd767 PS28, Line 142: static enum cb_err cse_send_backup_psr_cmd(struct psr_heci_fw_downgrade_backup_res *res) I don't think there is a lot of value having this as a dedicated function unless you have plan of using it for other purposes. https://review.coreboot.org/c/coreboot/+/74577/comment/866eea7c_1d7a04f3 PS28, Line 813: coding style: I don't think there is any rule requiring a blank link at the beginning of a block. And your patch seems to be introducing this. -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 28 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Comment-Date: Tue, 02 May 2023 18:09:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
by Jonathon Hall (Code Review) 02 May '23

02 May '23

Attention is currently required from: Paul Menzel, Angel Pons, Kyösti Mälkki, Felix Held. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74363 ) Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 ...................................................................... Patch Set 6: (1 comment) File src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c: https://review.coreboot.org/c/coreboot/+/74363/comment/440cec0b_d939aa03 PS5, Line 25: const pnp_devfn_t ec_rtct_dev = PNP_DEV(0x4E, IT8528E_RTCT); > Thank you, good catch! Checked this out, this base address is the default for the SuperIO, so the o […] Thanks, sounds like we should keep the bootblock config then. I fixed it to use port 0x2e and tested by manually setting this I/O BAR to some other value, then rebooted with this firmware, confirmed the cmos.default was applied correctly by bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/74363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 18:00:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2023