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Change subject: ec/starlabs/merlin: Change the fallback value for fn_ctrl_swap
......................................................................
Patch Set 1:
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Change subject: cpu/x86/reset16.S: Remove handcoded reset vector
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> why not?
Because nothing changed? 20 years ago there were toolchains that could
handle it. Now there's a toolchain too that can handle it. Doesn't say
anything about the next toolchain. We didn't have to change it for 19
years; changing it now makes it more likely that we'll have to change
it more often.
> or maybe: after 19 years someone finally change it!
> an improvement is an improvement ;)
What is improved exactly?
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74920 )
Change subject: soc/intel/common: Add an error for missing ramtop CMOS entry
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Set Ready For Review
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Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device()
......................................................................
Patch Set 4:
(1 comment)
File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/c6d34d4b_dd8c6436
PS4, Line 29: fadt->p_lvl3_lat = chip->c3_latency;
> > I wouldn't say the current implementation is right. But if we want to drop
> > Processor(), shouldn't we first have an alternative ready?
>
> Despite the removal of [WIP] I have no rush to get this in. Future OSPM still has to parse deprecated Processor(), right? If not, then this patch is better than nothing.
I guess that finding an OS in the future that still has support for (now)
15 years old machines and a brand new OSPM might be difficult. Also, general
purpose OS's would likely keep Processor() support as long as they want to
support such old machines because most of them won't get firmware updates.
IOW sometimes, not updating firmware can be more compatible. Because nobody
expects it.
But I'm not concerned about switching to _CST etc. That's been in OS's for
a long time already.
>
> > In any case, we shouldn't leave dead code around. AFAICT, this was the only
> > consumer of `c3_latency`.
>
> We also have _CST entries without C3, and _CST entries with C3 where latency does not match with the devicetree... Elsewhere I also popped the question, if it is valid to evaluate BSP MSR's to fill in AP _CST entries.
Probably not unconditionally. There can be boards with broken, low-power
c-states. So there should be an opt-out. And there's also a tradeoff
question, on mobile devices we might want the lowest power states, but
probably not on desktops.
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Hello build bot (Jenkins), Subrata Banik, Nico Huber, Arthur Heymans, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74432
to look at the new patch set (#10).
Change subject: mb/starlabs/starbook: Add ramtop to CMOS layout
......................................................................
mb/starlabs/starbook: Add ramtop to CMOS layout
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP
can be used.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7
---
M src/mainboard/starlabs/starbook/cmos.layout
M src/mainboard/starlabs/starbook/variants/tgl/cmos.layout
2 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/74432/10
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Change subject: cpu/x86/reset16.S: Remove handcoded reset vector
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> So after 19 years change it, but why? Did somebody miss the 2 bytes?
why not?
or maybe: after 19 years someone finally change it!
an improvement is an improvement ;)
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