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Change subject: soc/amd/mendocino: Add Kconfig option to generate manifest
......................................................................
Patch Set 5:
(2 comments)
Patchset:
PS5:
Why have a Kconfig option? Is there a reason not to just add this all the time?
If it does make sense to add a Kconfig file, why not default it to on?
Does it make sense to add this to other AMD platforms? If it does, maybe add (most of) this to the common Kconfig and Makefile? Obviously the option needs to be added to each platform's makefile individually.
File src/soc/amd/mendocino/Kconfig:
https://review.coreboot.org/c/coreboot/+/74267/comment/c821474a_35fa09be
PS5, Line 487: INCLUDE_MANIFEST_FILE
Can this be more specific? STORE_AMDFW_MANIFEST maybe?
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Change subject: amdfwtool: Add --output-manifest option
......................................................................
Patch Set 5:
(1 comment)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/74266/comment/f3c5f831_86d36e1c
PS5, Line 248: output_manifest
Why is this needed? Why not just set a flag to true? It just looks like this adds complexity that isn't needed right now.
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Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device()
......................................................................
Patch Set 4:
(2 comments)
File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/3fd026e7_3ec1cda8
PS4, Line 29: fadt->p_lvl3_lat = chip->c3_latency;
> Well, the question is if _CST is a property of the installed CPU part and the location of get_cst_en […]
I wouldn't say the current implementation is right. But if we want to drop
Processor(), shouldn't we first have an alternative ready?
In any case, we shouldn't leave dead code around. AFAICT, this was the only
consumer of `c3_latency`.
File src/southbridge/intel/i82801jx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/76aef374_b022ed28
PS4, Line 25: fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
> Deprecation of Processor() object hides C2/C3 IO "trap" addresses (PROC_CNT or PROC_BLK +4 (C2) and […]
Ok, I get it now. ACPI spec isn't very specific about this in the FADT description.
I missed that we don't advertise P_BLK anymore. Dropping these settings is fine
then.
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Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device()
......................................................................
Patch Set 4:
(1 comment)
File src/southbridge/intel/i82801jx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/906d361c_9701b04e
PS4, Line 25: fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
> Removing the FIXME probably won't get heads up. At least that's how I understand […]
Deprecation of Processor() object hides C2/C3 IO "trap" addresses (PROC_CNT or PROC_BLK +4 (C2) and +5 (C3)) from OSPM. If there is no _CST present, I see no mechanism to enter C2/C3 states?
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Change subject: mb/google/link: Apply symmetry for EC events defines
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/link/mainboard.c:
https://review.coreboot.org/c/coreboot/+/74602/comment/194971a3_84796b28
PS4, Line 111: mainboard_ec_init();
> looks like this is missing a declaration
Yeah, <ec/ec.h>, existing "ec.h" did not make it.
I'll get back to this mb-smihandler after tagged release.
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Change subject: mb/google/link: Apply symmetry for EC events defines
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/link/ec.h:
https://review.coreboot.org/c/coreboot/+/74602/comment/56b2cac9_8707a802
PS4, Line 38:
If I got it correctly, the defines from lines 39-41 should be kept and the API name should be changed. This is why a definition is missing in mainboard.c (line 111).
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Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device()
......................................................................
Patch Set 4:
(1 comment)
File src/southbridge/intel/i82801jx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/c6919fff_84199849
PS4, Line 25: fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
> Commit message hopefully raises enough eyebrows for someone to act on a fix without degraded perform […]
Removing the FIXME probably won't get heads up. At least that's how I understand
it, the patch doesn't effectively change the value, right? And that's where I see
it potentially disagreeing with the commit message.
But let me ask differently, what's the incentive to drop the FADT fallback values?
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Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device()
......................................................................
Patch Set 4:
(2 comments)
File src/southbridge/intel/i82801gx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/67e09efe_04835e1b
PS4, Line 29: fadt->p_lvl3_lat = chip->c3_latency;
> This leaves the `c3_latency` field blind. Would it be much hassle to port […]
Well, the question is if _CST is a property of the installed CPU part and the location of get_cst_entries() implementations under mb/ is wrong to begin with.
File src/southbridge/intel/i82801jx/fadt.c:
https://review.coreboot.org/c/coreboot/+/74441/comment/5025336c_ba6e8df2
PS4, Line 25: fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
> ACPI spec: "A value > 1000 indicates the system does not support a C3 state.". […]
Commit message hopefully raises enough eyebrows for someone to act on a fix without degraded performance / battery life.
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Change subject: security/tpm: Add Kconfig to allow payload control of TPM1
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Well, did you rewrite your payload to actually send the TPM_Startup command, then? I'm not saying th […]
currently, edk2 expects coreboot to have initialized the TPM and set up the necessary ACPI tables - it's just providing the front end to manage the TPM state / allow the user to confirm TPM changes initiated by the OS. The only problem which I'm trying to work around is coreboot force-enabling the TPM, since it prevents the user / edk2 from disabling/deactivating it.
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