coreboot-gerrit May 2023

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[M] Change in coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses
by Jonathon Hall (Code Review) 02 May '23

02 May '23

Attention is currently required from: Paul Menzel, Angel Pons, Kyösti Mälkki, Felix Held. Hello build bot (Jenkins), Paul Menzel, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74903 to look at the new patch set (#3). Change subject: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses ...................................................................... drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses Configure the CMOS bank I/O base addresses with PC_CMOS_BASE_PORT_BANK* rather than hard-coding as 0x70, 0x72. The defaults remain the same. Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/drivers/pc80/rtc/Kconfig M src/drivers/pc80/rtc/mc146818rtc.c M src/include/pc80/mc146818rtc.h 3 files changed, 37 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74903/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Gerrit-Change-Number: 74903 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: amdfwtool: Add --output-manifest option
by Paul Menzel (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Jakub Czapiga, Matt DeVillier, Grzegorz Bernacki, Arthur Heymans, Fred Reitberger, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74266 ) Change subject: amdfwtool: Add --output-manifest option ...................................................................... Patch Set 5: (2 comments) Commit Message: PS5: Please use the full width of 72 characters. Patchset: PS5: I still think, it would be better to just output it to stdout, and create the file using UNIX tools with `>` or `| tee` (redirection and/or pipes). -- To view, visit https://review.coreboot.org/c/coreboot/+/74266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Gerrit-Change-Number: 74266 Gerrit-PatchSet: 5 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 17:04:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [TEST] [Do Not Merge] Send EOP from payload
by Kapil Porwal (Code Review) 02 May '23

02 May '23

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74881 ) Change subject: [TEST] [Do Not Merge] Send EOP from payload ...................................................................... [TEST] [Do Not Merge] Send EOP from payload Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I542f06ad6bb0c34a1757da97dd8a63b052f39c0b --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/mainboard/google/rex/Kconfig M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c 10 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/74881/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 5f6a223..53637fe 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -80,6 +80,7 @@ CB_TAG_TCPA_LOG = 0x0036, CB_TAG_FMAP = 0x0037, CB_TAG_SMMSTOREV2 = 0x0039, + CB_TAG_CSE_EOP = 0x003b, CB_TAG_BOARD_CONFIG = 0x0040, CB_TAG_ACPI_CNVS = 0x0041, CB_TAG_TYPE_C_INFO = 0x0042, @@ -419,6 +420,12 @@ u32 type; }; +struct cb_cse_eop { + uint32_t tag; + uint32_t size; + void (*send)(void); +}; + /* * Handoff the ACPI RSDP */ diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 12d8a13..1bb64fe 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -159,6 +159,7 @@ uint32_t cbfs_ro_mcache_size; uintptr_t cbfs_rw_mcache_offset; uint32_t cbfs_rw_mcache_size; + struct cb_cse_eop *cse_eop; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index bcc9530..4edd1bf 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -277,6 +277,11 @@ info->acpi_rsdp = cb_acpi_rsdp->rsdp_pointer; } +static void cb_parse_cse_eop(void *ptr, struct sysinfo_t *info) +{ + info->cse_eop = (struct cb_cse_eop *)ptr; +} + int cb_parse_header(void *addr, int len, struct sysinfo_t *info) { struct cb_header *header; @@ -423,6 +428,9 @@ case CB_TAG_PCIE: cb_parse_pcie(ptr, info); break; + case CB_TAG_CSE_EOP: + cb_parse_cse_eop(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index e646b8b..a665209 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -82,6 +82,7 @@ LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, LB_TAG_SMMSTOREV2 = 0x0039, LB_TAG_TPM_PPI_HANDOFF = 0x003a, + LB_TAG_CSE_EOP = 0x003b, LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, LB_TAG_TYPE_C_INFO = 0x0042, @@ -572,4 +573,10 @@ lb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ }; +struct lb_cse_eop { + uint32_t tag; + uint32_t size; + void (*send)(void); +}; + #endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index e209e4b..5d33cd7 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -47,4 +47,6 @@ /* Add VBOOT VBNV offsets. */ void lb_table_add_vbnv_cmos(struct lb_header *header); +void lb_cse_send_eop_and_finalize(void); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index bee389d..1993fbe 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -464,6 +464,18 @@ return (uintptr_t)lb_table_fini(head) - entry; } +static void fill_cse_eop_info(struct lb_header *head) +{ + struct lb_cse_eop *lb_eop; + + lb_eop = (struct lb_cse_eop *)lb_new_record(head); + + lb_eop->tag = LB_TAG_CSE_EOP; + lb_eop->size = sizeof(*lb_eop); + + lb_eop->send = lb_cse_send_eop_and_finalize; +} + static uintptr_t write_coreboot_table(uintptr_t rom_table_end) { struct lb_header *head; @@ -560,6 +572,8 @@ if (CONFIG(HAVE_ACPI_TABLES)) lb_add_acpi_rsdp(head); + fill_cse_eop_info(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 528a2dc..073b5b4 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -27,7 +27,7 @@ select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 - select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD config BOARD_GOOGLE_BASEBOARD_REX def_bool n diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1eb3eff..98908a1 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -107,6 +107,16 @@ request is posted (at CSE .final device operation) and the time coreboot check for its completion (BS_PAYLOAD_LOAD). +config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + depends on !SOC_INTEL_CSE_SEND_EOP_LATE + depends on !SOC_INTEL_CSE_SEND_EOP_EARLY + depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC + help + Use this config to send End Of Post (EOP) using payload. coreboot supplies a function + pointer, to send EOP, to payload via a coreboot table. + config SOC_INTEL_CSE_LITE_SKU bool default n diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 1aa3454..8deef01 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1408,6 +1408,7 @@ void cse_late_finalize(void) { if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) && + !CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) && !CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) return; @@ -1434,6 +1435,7 @@ * will be run once the EOP command has successfully been completed. */ if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) || CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) return; diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index dd67e59..264f3c4 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <boot/coreboot_tables.h> #include <bootstate.h> #include <console/console.h> #include <intelblocks/cse.h> @@ -301,10 +302,22 @@ do_send_end_of_post(true); if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE) || + CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) || CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) cse_late_finalize(); } +void lb_cse_send_eop_and_finalize(void) +{ + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD)) + return; + + printk(BIOS_INFO, "Sending End-of-POST from the payload!\n"); + + send_cse_eop_with_late_finalize(NULL); +} + +#if !CONFIG(SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD) /* * Ideally, to give coreboot maximum flexibility, sending EOP would be done as * late possible. If HECI_DISABLE_USING_SMM is selected, then sending EOP must @@ -319,3 +332,4 @@ #else BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, send_cse_eop_with_late_finalize, NULL); #endif +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/74881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542f06ad6bb0c34a1757da97dd8a63b052f39c0b Gerrit-Change-Number: 74881 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses
by Jonathon Hall (Code Review) 02 May '23

02 May '23

Attention is currently required from: Paul Menzel, Angel Pons, Kyösti Mälkki, Felix Held. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74903 ) Change subject: drivers/pc80/rtc/mc146818rtc.c: Add Kconfig for RTC CMOS base addresses ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74903/comment/8c856dcd_b987fb01 PS2, Line 17: and the EC BRAM bank 1. > To me, this paragraph seems a bit unnecessary. […] That's fine, I just felt like I usually get asked to add more explanation of why someone might want this feature :D File src/drivers/pc80/rtc/Kconfig: https://review.coreboot.org/c/coreboot/+/74903/comment/d51ed452_f13c7dca PS2, Line 9: depends on DRIVERS_MC146818 > Should this be repeated or grouped under 'if' with added entries? Some files (drivers/pc80/rtc/option.c,post.c) include mc146818.h but don't depend on DRIVERS_MC146818, so the new configs are still relevant. -- To view, visit https://review.coreboot.org/c/coreboot/+/74903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44e5f5191c66f44e2df8ea0ff58a860be88bfcf Gerrit-Change-Number: 74903 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 16:45:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: amdfwtool: Add --output-manifest option
by Karthik Ramasubramanian (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Jakub Czapiga, Matt DeVillier, Paul Menzel, Grzegorz Bernacki, Arthur Heymans, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74266 ) Change subject: amdfwtool: Add --output-manifest option ...................................................................... Patch Set 5: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/74266/comment/83f6cf45_a01c4e8a PS5, Line 248: output_manifest > Why is this needed? Why not just set a flag to true? It just looks like this adds complexity that i […] A single approach to read the version does not work for all the blobs. This serves dual purpose - one as a flag that we want to capture the version for this blob and other as a mechanism regarding how to read the version. This way output_manifest function does not have blob specific checks and is simple to read. We can rename output_manifest as default_output_manifest which applies for majority of the blobs. -- To view, visit https://review.coreboot.org/c/coreboot/+/74266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6 Gerrit-Change-Number: 74266 Gerrit-PatchSet: 5 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 16:40:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
by Jonathon Hall (Code Review) 02 May '23

02 May '23

Attention is currently required from: Paul Menzel, Angel Pons, Kyösti Mälkki, Felix Held. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74363 ) Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 ...................................................................... Patch Set 5: (1 comment) File src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c: https://review.coreboot.org/c/coreboot/+/74363/comment/d103d522_77949787 PS5, Line 25: const pnp_devfn_t ec_rtct_dev = PNP_DEV(0x4E, IT8528E_RTCT); > Devicetree says 0x2e for the config space? Thank you, good catch! Checked this out, this base address is the default for the SuperIO, so the only part of this that is working is opening the LPC I/O range. I could either remove the init and assume it is at POR default or fix it to 0x2e. I suppose it would matter if rebooting from a firmware build that had configured it differently. But even the AMI firmware uses the default address so this is probably unlikely. What is the typical strategy for things like this? Assume it's at POR defaults or configure it explicitly? -- To view, visit https://review.coreboot.org/c/coreboot/+/74363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 5 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 16:38:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/speedstep: Use acpigen_write_processor_device()
by Kyösti Mälkki (Code Review) 02 May '23

02 May '23

Attention is currently required from: Nico Huber, Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74441 ) Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... Patch Set 4: (1 comment) File src/southbridge/intel/i82801gx/fadt.c: https://review.coreboot.org/c/coreboot/+/74441/comment/27db38f6_b840725b PS4, Line 29: fadt->p_lvl3_lat = chip->c3_latency; > I wouldn't say the current implementation is right. But if we want to drop > Processor(), shouldn't we first have an alternative ready? Despite the removal of [WIP] I have no rush to get this in. Future OSPM still has to parse deprecated Processor(), right? If not, then this patch is better than nothing. > In any case, we shouldn't leave dead code around. AFAICT, this was the only > consumer of `c3_latency`. We also have _CST entries without C3, and _CST entries with C3 where latency does not match with the devicetree... Elsewhere I also popped the question, if it is valid to evaluate BSP MSR's to fill in AP _CST entries. -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 02 May 2023 16:22:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Print content of manifest file
by Martin L Roth (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Jakub Czapiga, Matt DeVillier, Himanshu Sahdev, Paul Menzel, Grzegorz Bernacki, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74269 ) Change subject: soc/amd/mendocino: Print content of manifest file ...................................................................... Patch Set 5: (2 comments) File src/soc/amd/mendocino/manifest.c: https://review.coreboot.org/c/coreboot/+/74269/comment/5408a365_6a4c2eba PS3, Line 22: BS_PAYLOAD_LOAD > I am fine with dumping at this boot state. […] works for me. File src/soc/amd/mendocino/manifest.c: https://review.coreboot.org/c/coreboot/+/74269/comment/c79299fe_5c38a25f PS5, Line 14: printk(BIOS_ERR, "Failed to get amdfw_manifest\n"); Maybe change the print level to warn or info? I don't think this qualifies as an error. -- To view, visit https://review.coreboot.org/c/coreboot/+/74269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311 Gerrit-Change-Number: 74269 Gerrit-PatchSet: 5 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 16:15:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Print content of manifest file
by Martin L Roth (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Jakub Czapiga, Matt DeVillier, Himanshu Sahdev, Paul Menzel, Grzegorz Bernacki, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74269 ) Change subject: soc/amd/mendocino: Print content of manifest file ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Should we add the call to psp_verstage as well so we can see the RO versions? If we move code in the previous patch to common, can we move this too? We're going to want this on platforms going forward, so it doesn't seen like confining it to mdn is the right place. -- To view, visit https://review.coreboot.org/c/coreboot/+/74269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8df54b74cd987b4a3be635932d38ea178d0b0311 Gerrit-Change-Number: 74269 Gerrit-PatchSet: 5 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 May 2023 16:14:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Nick Vaccaro (Code Review) 02 May '23

02 May '23

Attention is currently required from: YH Lin, Tarun Tuli, Joey Peng, Paul Menzel, Eric Lai. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 11 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 May 2023 16:13:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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