coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Remove Soundwire workaround
by Sean Rhodes (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72669 ) Change subject: mb/starlabs/starbook/adl: Remove Soundwire workaround ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72669/comment/2eeae647_7b4edc03 PS5, Line 12: > `git blame` says commit 17441a3ac5a (mainboard/starlabs: Add StarBook Mk V) is when this workaround […] Right - it was in the original code -- To view, visit https://review.coreboot.org/c/coreboot/+/72669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Gerrit-Change-Number: 72669 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 03 Apr 2023 10:23:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Remove Soundwire workaround
by Sean Rhodes (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Sean Rhodes, Paul Menzel. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72669 to look at the new patch set (#6). Change subject: mb/starlabs/starbook/adl: Remove Soundwire workaround ...................................................................... mb/starlabs/starbook/adl: Remove Soundwire workaround This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc --- M src/mainboard/starlabs/starbook/acpi/mainboard.asl 1 file changed, 14 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/72669/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/72669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Gerrit-Change-Number: 72669 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Remove Soundwire workaround
by Angel Pons (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Sean Rhodes, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72669 ) Change subject: mb/starlabs/starbook/adl: Remove Soundwire workaround ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72669/comment/12b0a0d3_d5940916 PS5, Line 12: > It doesn't revert a commit `git blame` says commit 17441a3ac5a (mainboard/starlabs: Add StarBook Mk V) is when this workaround was added. -- To view, visit https://review.coreboot.org/c/coreboot/+/72669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Gerrit-Change-Number: 72669 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 03 Apr 2023 10:21:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: superiotool/ite.c: Add IT8784E support
by Michał Żygowski (Code Review) 03 Apr '23

03 Apr '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74172 ) Change subject: superiotool/ite.c: Add IT8784E support ...................................................................... superiotool/ite.c: Add IT8784E support IT8784E is basically a IT8786E stripped from serial ports 3-6. The are very few minor register differences in EC IO space and GPIO LDN, which are covered by this patch. Based on IT8784E-I Preliminary Specification V0.7.1 (non-public). TEST=Dump SIO configuration on Protectli VP4670 (vault_cml). Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5de8aeaff9697b854281391083f77a1083d12fe6 --- M util/superiotool/ite.c 1 file changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/74172/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 31fc496..c2d1583 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -1168,6 +1168,51 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x06,EOT}}, {EOT}}}, + {0x8784, "IT8784E-I", { + {NOLDN, NULL, + {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26, + 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, + EOT}, + {NANA,NANA,0x87,0x86,MISC,0x40,RSVD,0x00,0xf3, + 0x00,0x00,0x00,0x00,0x48,0x89,0x00,0x00,0x00, + EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x03,0xf8,0x04,0x00,0x50,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x62,0x63,0x70,0x74,0xf0,EOT}, + {0x00,0x03,0x78,0x07,0x78,0x07,0x03,0x03,EOT}}, + {0x4, "Environment controller", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xfa,0xfb,0xfd,EOT}, + {0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00, + 0x00,0x00,MISC,MISC,MISC,MISC,MISC,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x48,EOT}}, + {0x6, "Mouse", + {0x30,0x70,0x71,0xf0,EOT}, + {0x00,0x0c,0x02,0x00,EOT}}, + {0x7, "GPIO", + {0x60,0x61,0x62,0x63,0x70,0x71,0x72,0x73,0x74,0xb0, + 0xb1,0xb2,0xb3,0xb4,0xb8,0xb9,0xba,0xbb,0xbc,0xbd, + 0xc0,0xc1,0xc2,0xc3,0xc4,0xc8,0xc9,0xca,0xcb,0xcc, + 0xcd,0xce,0xcf,0xd1,0xd2,0xd3,0xd4,0xd6,0xd7,0xd8, + 0xd9,0xe0,0xe1,0xe2,0xe3,0xe4,0xe7,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x38,0x00,0x00, + 0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x40,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x03,0x10,0x0b,0x06,EOT}}, + {EOT}}}, {0x8786, "IT8786E-I", { {NOLDN, NULL, {0x02,0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26, @@ -1501,6 +1546,35 @@ 0x00,0x7f,0x7f,0x7f,0x7f,0x00,0x00,0x7f,MISC,0x00, 0x00,0x00,0x00,MISC,0x02,EOT}}, {EOT}}}, + {0x8784, "IT8784E-I", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x20,0x21,0x22,0x23,0x24,0x27,0x28,0x29,0x2a,0x2b, + 0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39, + 0x3e,0x3f,0x40,0x41,0x42,0x43,0x44,0x45,0x50,0x51, + 0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5b,0x5c, + 0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63,0x64,0x65,0x66, + 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x70,0x71,0x72, + 0x73,0x74,0x75,0x76,0x80,0x81,0x82,0x83,0x84,0x85, + 0x86,0x87,0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f, + 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99, + 0x9c,0x9d,0x9e,0x9f,0xc0,0xc1,0xc2,0xc3,0xc4,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0, + 0x44,0x0F,0x00,NANA,NANA,NANA,MISC,MISC,MISC,0x07, + 0x40,0x00,0x00,0x00,NANA,NANA,NANA,MISC,MISC,MISC, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC, + MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,0x00,0x00, + 0x7f,0x7f,0x7f,0x40,0x00,0x00,0x90,0x00,0x12,0x60, + 0x00,0x00,0x00,0x7f,0x7f,0x7f,0x80,0x00,0x7f,0x0f, + 0x7f,0x7f,0x7f,0x80,0x00,0x7f,0x0f,0x7f,0x7f,0x7f, + 0x80,0x00,0x7f,0x0f,NANA,NANA,NANA,NANA,MISC,MISC + MISC,MISC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA, + 0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,MISC,0x00, + 0x00,MISC,0x00,MISC,0x00,0x00,MISC,MISC,MISC,EOT}}, + {EOT}}}, {0x8786, "IT8786E-I", { {NOLDN, NULL, {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, -- To view, visit https://review.coreboot.org/c/coreboot/+/74172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de8aeaff9697b854281391083f77a1083d12fe6 Gerrit-Change-Number: 74172 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by cong yang (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Jianeng Ceng, Yidi Lin, Yu-Ping Wu. cong yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74115 ) Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 9 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 09:47:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "mb/starlabs/*: Remove sleepstates.asl"
by Sean Rhodes (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Benjamin Doron, Maximilian Brune, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73894 ) Change subject: Revert "mb/starlabs/*: Remove sleepstates.asl" ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Misses those, created PR and what not - S4 works on my ADL with it. […] Tried that patch on TGL, seems to assert on: ``` Loading driver CBD2E4D5-7068-4FF5-B462-9822B4AD8D60 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 763D8440 Loading driver at 0x0007676E000 EntryPoint=0x00076777EBF VariableRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 763D8998 ProtectUefiImageCommon - 0x763D8440 - 0x000000007676E000 - 0x0000000000011000 SetUefiImageMemoryAttributes - 0x000000007676E000 - 0x0000000000001000 (0x0000000000004000) SetUefiImageMemoryAttributes - 0x000000007676F000 - 0x000000000000E000 (0x0000000000020000) SetUefiImageMemoryAttributes - 0x000000007677D000 - 0x0000000000002000 (0x0000000000004000) PROGRESS CODE: V03040002 I0 VarCheckLibRegisterSetVariableCheckHandler - 0x767743B6 Success Variable driver common space: 0xFF9C 0xFF9C 0xFF9C DXE_ASSERT!: [VariableRuntimeDxe] /home/sean/Documents/coreboot/payloads/external/edk2/workspace/starlabsltd/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableNonVolatile.c (280): GetNonVolatileMaxVariableSize () < (VariableStoreLength - sizeof (VARIAB ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/73894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Gerrit-Change-Number: 73894 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 09:39:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/mayan: Update the DXIO descriptors for mayan
by Anand Vaikar (Code Review) 03 Apr '23

03 Apr '23

Anand Vaikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74191 ) Change subject: mb/amd/mayan: Update the DXIO descriptors for mayan ...................................................................... mb/amd/mayan: Update the DXIO descriptors for mayan Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/mayan/port_descriptors.c 1 file changed, 69 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/74191/1 diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c index f52abcd..19b4cd0 100644 --- a/src/mainboard/amd/mayan/port_descriptors.c +++ b/src/mainboard/amd/mayan/port_descriptors.c @@ -6,48 +6,87 @@ #include <soc/platform_descriptors.h> #include <types.h> -/* TODO: Update for mayan */ -static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { + +static fsp_dxio_descriptor mayan_dxio_descriptors[] = { { + // MXM .engine_type = PCIE_ENGINE, .port_present = true, .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 2, + .end_logical_lane = 3, + .device_number = 1, .function_number = 1, - .link_speed_capability = GEN3, + .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ3, + .link_aspm_L1_1 = 1, + .link_aspm_L1_2 = 1, + .link_hotplug = 0, + .gpio_group_id = 4, + .clk_pm_support = 1, + .clk_req = CLK_REQ0, + .eq_preset = 3, + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} }, { + // M2 SSD0-NVME .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, + .start_logical_lane = 16, + .end_logical_lane = 19, + .device_number = 2, + .function_number = 4, + .link_speed_capability = GEN_MAX, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_aspm_L1_1 = 1, + .link_aspm_L1_2 = 1, + .link_hotplug = 0, + .gpio_group_id = 27, + .clk_pm_support = 1, + .clk_req = CLK_REQ4, + .eq_preset = 3, + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} + }, + { + // X1 + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 15, + .end_logical_lane = 15, .device_number = 2, .function_number = 2, - .link_speed_capability = GEN3, + .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, .link_aspm = 2, - .link_hotplug = 3, - .clk_req = CLK_REQ1, + .link_aspm_L1_1 = 1, + .link_aspm_L1_2 = 1, + .link_hotplug = 0, + //.gpio_group_id = 30, + .clk_pm_support = 1, + .clk_req = CLK_REQ6, + .eq_preset = 3, + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} }, { + // DT .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 3, - .device_number = 2, - .function_number = 3, - .link_speed_capability = GEN3, + .start_logical_lane = 8, + .end_logical_lane = 9, + .device_number = 1, + .function_number = 2, + .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, .link_aspm = 2, - .link_hotplug = 3, - .gpio_group_id = GPIO_27, - .clk_req = CLK_REQ0, + .link_aspm_L1_1 = 1, + .link_aspm_L1_2 = 1, + .link_hotplug = 0, + .clk_pm_support = 0, + .clk_req = CLK_REQ1, + .eq_preset = 3, + .port_params = {PP_PSPP_AC, 0x144, PP_PSPP_DC, 0x133} }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/74191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e Gerrit-Change-Number: 74191 Gerrit-PatchSet: 1 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmn: Implement HECI commands to get version details of ISHC
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmn: Implement HECI commands to get version details of ISHC ...................................................................... Patch Set 11: (6 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74005/comment/eca608f4_8aa16853 PS11, Line 204: saved_version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(fw_partition_version)); > ideally this should be cbmem_find() and if find is failing then you should add new entry isn't it. > > cbmem_find() will pass for all consecutive boot and cbmem_add() is required only for first boot. while adding cbmem_add for the first time, u should store the initial value as NULL aka 0 and ishc_version_update_done as false. https://review.coreboot.org/c/coreboot/+/74005/comment/4d6425ee_1b8854ca PS11, Line 210: ishc_update_required saved_version->ishc_version_update_done = false https://review.coreboot.org/c/coreboot/+/74005/comment/7db6ceac_48bc613c PS11, Line 212: ishc_update_required assuming ishc_version_update_done is already set to `true` from since last update? File src/soc/intel/common/block/cse/cse_partition_version.c: https://review.coreboot.org/c/coreboot/+/74005/comment/bddd0b55_41b72106 PS11, Line 37: printk(BIOS_ERR, "HECI: ISHC version resp Failed: 0x%x\n", resp.hdr.result); while failing, u should mark ishc_version_update_done is false to avoid getting any wrong value https://review.coreboot.org/c/coreboot/+/74005/comment/30df3ad0_3b037cfd PS11, Line 40: ishc_update_required ishc_version_update_done=true File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/74005/comment/e5b12436_b2bd2112 PS11, Line 140: ishc_update_required ishc_version_update_done -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 11 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 08:59:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn: Implement HECI commands to get version details of ISHC
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmn: Implement HECI commands to get version details of ISHC ...................................................................... Patch Set 11: (10 comments) Patchset: PS11: can you please also create an API as an incremental patch named `get_ishc_version()` which will get called from ramstage alone and if return value version from cbmem if ishc_version_update_done is set to true. File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74005/comment/7ca62cc0_9ca3bdfb PS9, Line 204: Two instances of 'fw_version' were allocated to store both the ISHC and CSE versions. : The first instance will store ISHC version and the second instance will store CSE version : */ follow the may char per line rule File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74005/comment/6f90aa84_ad742a44 PS11, Line 204: saved_version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(fw_partition_version)); ideally this should be cbmem_find() and if find is failing then you should add new entry isn't it. cbmem_find() will pass for all consecutive boot and cbmem_add() is required only for first boot. https://review.coreboot.org/c/coreboot/+/74005/comment/121d90df_85c44d92 PS11, Line 206: // Compare if saved CSE is same as current follow /* */ https://review.coreboot.org/c/coreboot/+/74005/comment/e0999b5d_b0692c81 PS11, Line 211: else else { } File src/soc/intel/common/block/cse/cse_partition_version.c: https://review.coreboot.org/c/coreboot/+/74005/comment/d2d9e2a1_2166a2a6 PS11, Line 11: cbmem_entry_start shouldn't this be just cbmem_find() https://review.coreboot.org/c/coreboot/+/74005/comment/fbc40907_c3d664bd PS11, Line 36: if (ret || resp.hdr.result) if { } https://review.coreboot.org/c/coreboot/+/74005/comment/538306d6_e2a8d798 PS11, Line 44: BS_DEV_ENABLE if we want to do this operation at early ramstage then `BS_PRE_DEVICE` is the correct BS File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/74005/comment/f921f6b3_6bac77f7 PS11, Line 139: typedef avoid typedef https://review.coreboot.org/c/coreboot/+/74005/comment/18a48523_c6b95a23 PS11, Line 143: fw_partition_version cse_fw_ish_version_info -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 11 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 08:55:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/wwan/fm: Add ACPI power management for Fibocom modem
by build bot (Jenkins) (Code Review) 03 Apr '23

03 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74169 ) Change subject: drivers/wwan/fm: Add ACPI power management for Fibocom modem ...................................................................... Patch Set 1: (1 comment) File src/drivers/wwan/fm/acpi_fm350gl.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172911): https://review.coreboot.org/c/coreboot/+/74169/comment/a8077e8e_6fcbd6a3 PS1, Line 243: if (wwan_fm350gl_get_rtd3_method_support(config)) { suspicious code indentation after conditional statements -- To view, visit https://review.coreboot.org/c/coreboot/+/74169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9024ec420425c5bf7d0605e961d08afe6f15eda6 Gerrit-Change-Number: 74169 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Apr 2023 08:51:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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