coreboot-gerrit April 2023

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[M] Change in coreboot[master]: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73713 ) Change subject: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Gerrit-Change-Number: 73713 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:14:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by cong yang (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Paul Menzel, Jianeng Ceng, Yidi Lin, Yu-Ping Wu. cong yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74115 ) Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/geralt/panel_geralt.c: https://review.coreboot.org/c/coreboot/+/74115/comment/b2a734d9_a8c2276c PS9, Line 65: .name = "MUTTO_B152731E1", > Why replace this? Geralt is uses Samsung panel, and Mutto is responsible for bonding the panel and touch. It seems more appropriate to use the Samsung name. -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 9 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:03:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74161 ) Change subject: soc/intel/meteorlake: Enable VMX ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74161/comment/b46bde7d_57a60546 PS3, Line 7: soc/intel/meteorlake: Enable VMX Yes, reading the commit messages of all the change-sets, it’s clear. Commit messages should be self-contained, and only reading this commit message leaves a lot of questions open. Maybe: > soc/intel/meteorlake: Enable VMX in coreboot if not done by FSP https://review.coreboot.org/c/coreboot/+/74161/comment/833d74f7_b32e4a52 PS3, Line 9: This function calls into `set_feature_ctrl_vmx_arg()` : to enable VMX for virtualization. This should also be elaborated. https://review.coreboot.org/c/coreboot/+/74161/comment/4d5c7ad0_f381cc1d PS3, Line 11: > > I think it was discussed in the past, that coreboot does not need to do it, but it looks like ther […] I think I was remembering the commit message of commit 305b19dd7a83 (Remove code that enables/disables VMX in coreboot on chromebooks.) [1]. [1]: https://review.coreboot.org/c/coreboot/+/1276 -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:48:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: override Markarth PCIe config
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: John Su, Jason Nien, Chris Wang, Martin Roth, Karthik Ramasubramanian, Patrick Huang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74133 ) Change subject: mb/google/skyrim: override Markarth PCIe config ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74133/comment/bba478e1_d06efa32 PS3, Line 7: mb/google/skyrim Shouldn’t variant names be mentioned in the prefix? https://review.coreboot.org/c/coreboot/+/74133/comment/09b14e21_bdf2f689 PS3, Line 8: I’d start by describing the problem. Do you have a non-working test device? Or did you just check the schematics? https://review.coreboot.org/c/coreboot/+/74133/comment/3285033b_399edf22 PS3, Line 9: We lowercase: we https://review.coreboot.org/c/coreboot/+/74133/comment/30bd1920_adadac36 PS3, Line 12: allows allowing https://review.coreboot.org/c/coreboot/+/74133/comment/8cce2c22_83961b59 PS3, Line 17: TEST=emerge-skyrim coreboot chromeos-bootimage Did you test this on a real device? -- To view, visit https://review.coreboot.org/c/coreboot/+/74133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Gerrit-Change-Number: 74133 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Lean Sheng Tan, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Lean Sheng Tan, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74158 to look at the new patch set (#4). Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ...................................................................... soc/intel/cmn/cpu: Add function to disable 3-strike CATERR In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing, which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74158/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Lean Sheng Tan, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 ) Change subject: soc/intel/cmn/cpu: API to disable 3-strike Machine Check CAT error ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74158/comment/4f23dc73_e229f58a PS3, Line 7: API to disable 3-strike Machine Check CAT error > Please make it a statement by adding a verb (in imperative mood). […] Ack https://review.coreboot.org/c/coreboot/+/74158/comment/9dd79cdc_ddeae851 PS3, Line 8: > Please describe the problem, including what CAT means, and maybe a reference to the documentation of that counter. Added ample details. there are more material available online that talks about CATERR https://review.coreboot.org/c/coreboot/+/74158/comment/ad9e34b5_ccfada54 PS3, Line 10: would help > helps Ack https://review.coreboot.org/c/coreboot/+/74158/comment/cf8b7330_033a961b PS3, Line 9: This patch prevents the Three Strike Counter from incrementing, : which would help to disable Machine Check Catastrophic error. : It will provide more opportunity to collect more useful CPU : traces for debugging. > Please use the fully allowed text width of 72 characters per line. Ack File src/soc/intel/common/block/include/intelblocks/cpulib.h: https://review.coreboot.org/c/coreboot/+/74158/comment/79ec7cbe_0fa53066 PS3, Line 227: , > . Ack https://review.coreboot.org/c/coreboot/+/74158/comment/39db6324_3247a82a PS3, Line 228: it will help > It helps Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Gerrit-Change-Number: 74158 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:32:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Jianeng Ceng, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74115 ) Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/geralt/panel_geralt.c: https://review.coreboot.org/c/coreboot/+/74115/comment/36f15239_d78a1712 PS9, Line 65: .name = "MUTTO_B152731E1", Why replace this? -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 9 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:12:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: pci: Add support for assigning resources to SR-IOV VF BARs
by Name of user not set (Code Review) 03 Apr '23

03 Apr '23

stephend(a)silicom-usa.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages like: pci 0000:03:00.0: BAR 7: no space for [mem size 0x00100000 64bit] pci 0000:03:00.0: BAR 7: failed to assign [mem size 0x00100000 64bit] Tested on Camelback Mountain, and Harcuvar. Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 4 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..c96fc8d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -439,6 +439,11 @@ { pci_read_bases(dev, 6); pci_get_rom_resource(dev, PCI_ROM_ADDRESS); + +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) + /* Check for SR-IOV BARs if we have PCIe support */ + pciexp_dev_read_resources(dev); +#endif } void pci_bus_read_resources(struct device *dev) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..8d660b1 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -442,6 +442,82 @@ pciexp_enable_aspm(root, root_cap, dev, cap); } +/* + * Check if this is an SR-IOV capable device and add resources for all VF bars + * + * @param dev Pointer to the dev structure. + */ +void pciexp_dev_read_resources(struct device *dev) +{ + unsigned long sriovpos; + u16 numvfs, i; + + sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!sriovpos) { + return; + } + + sriovpos = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriovpos) { + return; + } + + numvfs = pci_read_config16(dev, sriovpos + PCI_SRIOV_TOT_VFS); + printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs); + + /* The spec allows this to be 0 for some reason. Nothing to do. */ + if (numvfs == 0) { + return; + } + + for (int off = 0; off < 6; off++) { + unsigned long res_ix = sriovpos + PCI_SRIOV_VFBAR0 + off * 4; + struct resource *resource; + + resource = pci_get_resource(dev, res_ix); + + /* VF BARs aren't necessarily contiguous, skip the unused ones */ + if (resource->size == 0) { + continue; + } + + printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n", + dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32, + resource->size, resource->index); + + if (resource->flags & IORESOURCE_PCI64) { + off++; + } + + /* + * SR-IOV BARs break the resource allocator assumption for PCI + * dev resources that size = gran = alignment. + * + * alignment = gran = pci_get_resource() result, but... + * size is pci_get_resource()->size * numvfs, and there's no + * power of two guarantee on size either since numvfs is just + * an integer. + * + * Rather than add code to handle this as a special case in the + * resource allocator, just round up the size. In practice + * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced + * should only be the size of a single VF BAR + */ + for (i = 1; i < numvfs; i <<= 1) { + resource->size <<= 1; + resource->align += 1; + resource->gran += 1; + } + + if (i != numvfs) { + printk(BIOS_DEBUG, "%s: VFs != 2^n, wasting MMIO space...\n", + dev_path(dev)); + } + } + + compact_resources(dev); +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..39a6137 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -453,6 +453,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_SRIOV 0x0010 /* Extended Capability lists*/ #define PCIE_EXT_CAP_OFFSET 0x100 @@ -518,6 +519,34 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ +/* SR-IOV */ +#define PCI_SRIOV_CAPS 0x04 /* SR-IOV capabilities */ +#define PCI_SRIOV_VF_MIG (1 << 0) /* VF Migration capable */ +#define PCI_SRIOV_ARI_CAP (1 << 1) /* ARI Capable Hierarchy Preserved */ +#define PCI_SRIOV_MIG_INT(x) (((x) >> 21) & 0x7ff) +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_VF_EN (1 << 0) +#define PCI_SRIOV_MIG_EN (1 << 1) +#define PCI_SRIOV_MIG_INT_EN (1 << 2) +#define PCI_SRIOV_MSE (1 << 3) +#define PCI_SRIOV_ARI_CAP_EN (1 << 4) +#define PCI_SRIOV_STATUS 0x0A /* SR-IOV Status */ +#define PCI_SRIOV_INIT_VFS 0x0C +#define PCI_SRIOV_TOT_VFS 0x0E +#define PCI_SRIOV_NUM_VFS 0x10 +#define PCI_SRIOV_FN_DEP_LINK 0x12 +#define PCI_SRIOV_VF_OFF 0x14 +#define PCI_SRIOV_VF_STRIDE 0x16 +#define PCI_SRIOV_VF_DEVID 0x1A +#define PCI_SRIOV_SUP_PAGE_SIZE 0x1C +#define PCI_SRIOV_PAGE_SIZE 0x20 +#define PCI_SRIOV_VFBAR0 0x24 +#define PCI_SRIOV_VFBAR1 0x28 +#define PCI_SRIOV_VFBAR2 0x2C +#define PCI_SRIOV_VFBAR3 0x30 +#define PCI_SRIOV_VFBAR4 0x34 +#define PCI_SRIOV_VFBAR5 0x38 +#define PCI_SRIOV_MIG_ARRAY 0x3C /* * The PCI interface treats multi-function devices as independent diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d..94a80bf 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -19,6 +19,8 @@ /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 +void pciexp_dev_read_resources(struct device *dev); + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 1 Gerrit-Owner: stephend(a)silicom-usa.com Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: arch/x86/smbios: Check str for NULL in smbios_add_string()
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Maximilian Brune. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73980 ) Change subject: arch/x86/smbios: Check str for NULL in smbios_add_string() ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/73980/comment/6d9ebf6a_7dca61aa PS2, Line 48: if (str == NULL || *str == '\0') > Done Thank you for sharing your perspective. (Maybe add it to the commit message.) -- To view, visit https://review.coreboot.org/c/coreboot/+/73980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic228b869aea362c1f07e0808c2735ff3b285a6bd Gerrit-Change-Number: 73980 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:11:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: arch/x86/smbios: Fix file formatting
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Angel Pons, Utkarsh Verma. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74170 ) Change subject: arch/x86/smbios: Fix file formatting ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/74170/comment/a4b98f04_96516ff0 PS2, Line 216: dimm->serial[1], dimm->serial[2], dimm->serial[3]); > Yes, I understand that and agree with it too. […] Utkarsh, just to let you know, that clang-format is not used yet in coreboot properly, so it might be too controversial or too much work. Of course, work on improving the situation by updating `.clang-format` is much appreciated. Only you can decide, if you want to open this Pandora’s box. -- To view, visit https://review.coreboot.org/c/coreboot/+/74170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f44eec4d14d8b905f438c5305b640a33408c45 Gerrit-Change-Number: 74170 Gerrit-PatchSet: 3 Gerrit-Owner: Utkarsh Verma <utkarsh(a)bitbanged.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Utkarsh Verma <utkarsh(a)bitbanged.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 11:10:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Utkarsh Verma <utkarsh(a)bitbanged.com> Gerrit-MessageType: comment

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