coreboot-gerrit April 2023

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[S] Change in coreboot[master]: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: cong yang, Jianeng Ceng, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74115 ) Change subject: mb/google/geralt: Power on Samsung ATNA33XC20 eDP panel ...................................................................... Patch Set 9: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74115/comment/93fa2273_bc420412 PS9, Line 2: cengjianeng Please update your user name to not be the username. $ git config --global user.name "Ceng …" $ git commit --amend --author="Ceng … <…>" -s https://review.coreboot.org/c/coreboot/+/74115/comment/b5922972_c81667da PS9, Line 29: cengjianeng Please update the spelling. File src/mainboard/google/geralt/panel_geralt.c: https://review.coreboot.org/c/coreboot/+/74115/comment/20bd42d9_80aa4f4f PS9, Line 65: .name = "MUTTO_B152731E1", > Geralt is uses Samsung panel, and Mutto is responsible for bonding the panel and touch. […] Thank you for the quick reply. Please mention that in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/74115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Gerrit-Change-Number: 74115 Gerrit-PatchSet: 9 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:29:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/alderlake: Add support for CSE timestamp data versions
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Wonkyu Kim. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73712 ) Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions ...................................................................... Patch Set 7: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/73712/comment/11093bbd_5764ab6e PS7, Line 10: Alderlake/Raptorlake Alder Lake/Raptor Lake https://review.coreboot.org/c/coreboot/+/73712/comment/6f672228_3ddaa30b PS7, Line 10: Meteorlake Meteor Lake File src/soc/intel/common/block/cse/Kconfig: https://review.coreboot.org/c/coreboot/+/73712/comment/3f3f1ff3_6bb9bd5e PS7, Line 200: ADL and RPL I’d spell it out. https://review.coreboot.org/c/coreboot/+/73712/comment/5e7bceb9_4b271507 PS7, Line 207: MTL-M/P Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/73712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Gerrit-Change-Number: 73712 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:28:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/arch/ Fixed some linter warnings and errors
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Philipp Hug, Philipp M, Julius Werner, ron minnich, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74173 ) Change subject: src/arch/ Fixed some linter warnings and errors ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74173/comment/6a0abf11_ec525de4 PS1, Line 7: Fixed Fix linter warnings and errors [1]: https://cbea.ms/git-commit/ https://review.coreboot.org/c/coreboot/+/74173/comment/2fca1327_0d910c80 PS1, Line 7: src/arch/ Fixed some linter warnings and errors Maybe split the commit into three: arch/arm*, arch/riscv, console. https://review.coreboot.org/c/coreboot/+/74173/comment/75def38e_ddecd260 PS1, Line 9: This is my first commit to coreboot, so please tell me if I'm missing something. > Possible unwrapped commit description (prefer a maximum 72 chars per line) Please fix. https://review.coreboot.org/c/coreboot/+/74173/comment/8fb79e24_fed7f343 PS1, Line 9: This is my first commit to coreboot, so please tell me if I'm missing something. Welcome to coreboot. This could be added as a comment, but does not belong into the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/74173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I976cffe971695f591ec42fce46e6743444277759 Gerrit-Change-Number: 74173 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp M Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Philipp M Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:25:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_emp
by Felix Held (Code Review) 03 Apr '23

03 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74142 ) Change subject: mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_emp ...................................................................... mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_emp Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/constitution/overridetree.cb 1 file changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index 67684b9..4b894b0 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -22,6 +22,19 @@ register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 + register "usb3_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A0 + register "usb3_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_de_emp = 0x2B, + .tx_downscale_amp = 0x00, + }" # Type-A port A1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI-IN register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port A3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Gerrit-Change-Number: 74142 Gerrit-PatchSet: 3 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pablo Ceballos <pceballos(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current values
by Felix Held (Code Review) 03 Apr '23

03 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74046 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current values ...................................................................... soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current values The Intel Power and Performance (PnP) team requested to update the following: - TDC settings for RPL-U 15W variant should be 22A. - TDC settings for RPL-P 28W variant should be 33A. BUG=b:275694022 BRANCH=firmware-brya-14505.B TEST=PnP validated performance impact with these settings on both RPL-U 15W and RPL-P 28W Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 32 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Baieswara Reddy Sagili: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index cfd0476..597f8c5 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -80,13 +80,13 @@ * + +-----------+-------+-------+---------+-------------+----------+ * | | GT | 3.2 | 3.2 | 55 | 86 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ - * | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 54 | 28000 | + * | RPL-P 482(28W) | IA | 2.3 | 2.3 | 102 | 33 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ - * | | GT | 3.2 | 3.2 | 55 | 54 | 28000 | + * | | GT | 3.2 | 3.2 | 55 | 33 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ - * | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 41 | 28000 | + * | RPL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 22 | 28000 | * + +-----------+-------+-------+---------+-------------+----------+ - * | | GT | 3.2 | 3.2 | 40 | 41 | 28000 | + * | | GT | 3.2 | 3.2 | 40 | 22 | 28000 | * +----------------+-----------+-------+-------+---------+-------------+----------+ */ @@ -245,10 +245,10 @@ { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, - { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) }, - { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, - { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, - { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, + { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, + { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, -- To view, visit https://review.coreboot.org/c/coreboot/+/74046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Gerrit-Change-Number: 74046 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/variants/hades: Add CPU power limits
by Felix Held (Code Review) 03 Apr '23

03 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73895 ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/variants/hades: Add CPU power limits ...................................................................... mb/google/brya/variants/hades: Add CPU power limits Add CPU power limits support and values for RPL on Hades BUG=b:269371363 TEST=builds Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc A src/mainboard/google/brya/variants/baseboard/hades/ramstage.c M src/mainboard/google/brya/variants/hades/Makefile.inc A src/mainboard/google/brya/variants/hades/ramstage.c 4 files changed, 87 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc index fd45b94..7c75e20 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc +++ b/src/mainboard/google/brya/variants/baseboard/hades/Makefile.inc @@ -1 +1,2 @@ romstage-y += memory.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c new file mode 100644 index 0000000..4858eb7 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include <drivers/intel/dptf/chip.h> +#include <intelblocks/power_limit.h> + +WEAK_DEV_PTR(dptf_policy); + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + if (!num_entries) + return; + + const struct device *policy_dev = DEV_PTR(dptf_policy); + if (!policy_dev) + return; + + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + u8 tdp = get_cpu_tdp(); + + for (size_t i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + struct dptf_power_limits *settings = &config->controls.power_limits; + config_t *conf = config_of_soc(); + struct soc_power_limits_config *soc_config = conf->power_limits_config; + settings->pl1.min_power = limits[i].pl1_min_power; + settings->pl1.max_power = limits[i].pl1_max_power; + settings->pl2.min_power = limits[i].pl2_min_power; + settings->pl2.max_power = limits[i].pl2_max_power; + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, + MILLIWATTS_TO_WATTS); + printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); + } + } +} diff --git a/src/mainboard/google/brya/variants/hades/Makefile.inc b/src/mainboard/google/brya/variants/hades/Makefile.inc index 2fa692a..837101e 100644 --- a/src/mainboard/google/brya/variants/hades/Makefile.inc +++ b/src/mainboard/google/brya/variants/hades/Makefile.inc @@ -1,3 +1,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/hades/ramstage.c b/src/mainboard/google/brya/variants/hades/ramstage.c new file mode 100644 index 0000000..e42b8ea --- /dev/null +++ b/src/mainboard/google/brya/variants/hades/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* Following values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7 Gerrit-Change-Number: 73895 Gerrit-PatchSet: 11 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power*
by Felix Held (Code Review) 03 Apr '23

03 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67061 ) Change subject: arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power* ...................................................................... arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power* CBFS location in memory is different than on the real hardware. Change-Id: Icd806a57f449042c883b624056c05c1ff7e4c17e Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67061 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/arch/ppc64/Makefile.inc M src/mainboard/emulation/qemu-power8/Makefile.inc R src/mainboard/emulation/qemu-power8/rom_media.c M src/mainboard/emulation/qemu-power9/Makefile.inc C src/mainboard/emulation/qemu-power9/rom_media.c 5 files changed, 22 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michał Kopeć: Looks good to me, approved diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 8ccd62b..92b1e39 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -12,7 +12,6 @@ bootblock-y = bootblock_crt0.S bootblock-y += arch_timer.c bootblock-y += boot.c -bootblock-y += rom_media.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -38,7 +37,6 @@ romstage-y += arch_timer.c romstage-y += boot.c romstage-y += stages.c -romstage-y += rom_media.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -64,7 +62,6 @@ ################################################################################ ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y) -ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += arch_timer.c ramstage-y += boot.c diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index 4011983..c1484b9 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -2,8 +2,11 @@ bootblock-y += bootblock.c bootblock-y += uart.c +bootblock-y += rom_media.c romstage-y += cbmem.c romstage-y += romstage.c ramstage-y += timer.c romstage-y += uart.c +romstage-y += rom_media.c ramstage-y += uart.c +ramstage-y += rom_media.c diff --git a/src/arch/ppc64/rom_media.c b/src/mainboard/emulation/qemu-power8/rom_media.c similarity index 100% rename from src/arch/ppc64/rom_media.c rename to src/mainboard/emulation/qemu-power8/rom_media.c diff --git a/src/mainboard/emulation/qemu-power9/Makefile.inc b/src/mainboard/emulation/qemu-power9/Makefile.inc index ace00a7..a71c20f 100644 --- a/src/mainboard/emulation/qemu-power9/Makefile.inc +++ b/src/mainboard/emulation/qemu-power9/Makefile.inc @@ -1,6 +1,10 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-y += rom_media.c + romstage-y += cbmem.c romstage-y += romstage.c +romstage-y += rom_media.c ramstage-y += ramstage.c +ramstage-y += rom_media.c diff --git a/src/arch/ppc64/rom_media.c b/src/mainboard/emulation/qemu-power9/rom_media.c similarity index 100% copy from src/arch/ppc64/rom_media.c copy to src/mainboard/emulation/qemu-power9/rom_media.c -- To view, visit https://review.coreboot.org/c/coreboot/+/67061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd806a57f449042c883b624056c05c1ff7e4c17e Gerrit-Change-Number: 67061 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threads
by Felix Singer (Code Review) 03 Apr '23

03 Apr '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74156 ) Change subject: util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threads ...................................................................... util/crossgcc/buildgcc: Allow bootstrapping CMake with multiple threads The main build process already runs multi-threaded, when requested. Apply the same setting to the bootstrap / configure step. Change-Id: I89d6728a0985946b702f83770bedf767afb12690 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74156 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/crossgcc/buildgcc 1 file changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 391d801..4f13606 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -893,6 +893,7 @@ build_CMAKE() { CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" \ ../${CMAKE_DIR}/configure \ + --parallel=${THREADS} \ --prefix="$TARGETDIR" || touch .failed # shellcheck disable=SC2086 $MAKE $JOBS || touch .failed -- To view, visit https://review.coreboot.org/c/coreboot/+/74156 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89d6728a0985946b702f83770bedf767afb12690 Gerrit-Change-Number: 74156 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/google/nissa/var/uldren: Add overridetree
by Felix Held (Code Review) 03 Apr '23

03 Apr '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73974 ) Change subject: mb/google/nissa/var/uldren: Add overridetree ...................................................................... mb/google/nissa/var/uldren: Add overridetree Add override devicetree based on schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Signed-off-by: Van Chen <van_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: John Su <john_su(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/uldren/include/variant/gpio.h M src/mainboard/google/brya/variants/uldren/overridetree.cb 4 files changed, 341 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved John Su: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Ian Feng: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 0080400..1534a54 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -160,6 +160,7 @@ default 0x1 if BOARD_GOOGLE_AURASH default 0x1 if BOARD_GOOGLE_HADES default 0x0 if BOARD_GOOGLE_YAVILLA + default 0x0 if BOARD_GOOGLE_ULDREN config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 706fdfd..fb8bb5e 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -361,6 +361,8 @@ config BOARD_GOOGLE_ULDREN bool "-> Uldren" select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_I2C_CS42L42 + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_YAVILLA bool "-> Yavilla" diff --git a/src/mainboard/google/brya/variants/uldren/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldren/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/uldren/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/uldren/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb index 4f2c04a..dbe46ed 100644 --- a/src/mainboard/google/brya/variants/uldren/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb @@ -1,6 +1,316 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + + register "tcss_aux_ori" = "5" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""WDHT0002"" + register "generic.desc" = ""WDT Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "130" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "detect" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "reset_delay_ms" = "20" + register "reset_off_delay_ms" = "2" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "stop_delay_ms" = "280" + register "stop_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "300" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 16 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7996"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "100" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "300" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "100" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "30" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "30" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + end + device ref i2c3 on + chip drivers/i2c/cs42l42 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)" + register "ts_inv" = "true" + register "ts_dbnc_rise" = "RISE_DEB_1000_MS" + register "ts_dbnc_fall" = "FALL_DEB_0_MS" + register "btn_det_init_dbnce" = "100" + register "btn_det_event_dbnce" = "10" + register "bias_lvls[0]" = "15" + register "bias_lvls[1]" = "8" + register "bias_lvls[2]" = "4" + register "bias_lvls[3]" = "1" + register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_disable" = "true" + device i2c 48 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7863"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 User Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 World Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on end + end + end + end + end end - end -- To view, visit https://review.coreboot.org/c/coreboot/+/73974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Gerrit-Change-Number: 73974 Gerrit-PatchSet: 10 Gerrit-Owner: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[master]: superio/ite: Add IT8784E support
by build bot (Jenkins) (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74174 ) Change subject: superio/ite: Add IT8784E support ...................................................................... Patch Set 1: (16 comments) File src/superio/ite/it8784e/acpi/superio.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/55562263_ef67a24e PS1, Line 33: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/1a77fc87_69d635ec PS1, Line 36: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/22316005_32c5f658 PS1, Line 38: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/644c9bfc_581d74b7 PS1, Line 43: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/90be7cd1_98001345 PS1, Line 46: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/5964c9b9_0f156be6 PS1, Line 58: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/facb48db_b6145f28 PS1, Line 61: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/e1023f8a_4f7875e2 PS1, Line 64: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/cddde0c1_da2ba406 PS1, Line 71: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/6d784dd2_b0da49d2 PS1, Line 75: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/e24688ff_ddb7a455 PS1, Line 83: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/15eef413_37afb305 PS1, Line 100: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/3e99b821_fc9b3815 PS1, Line 110: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/5fcb4eea_9af84076 PS1, Line 120: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/1711ef51_00e5f650 PS1, Line 140: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172934): https://review.coreboot.org/c/coreboot/+/74174/comment/b9681d53_4cd0e9a3 PS1, Line 152: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/74174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e Gerrit-Change-Number: 74174 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:16:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2023