coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mainboard/protectli/vault_cml: Switch to IT8784E
by Michał Żygowski (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Piotr Król. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74175 ) Change subject: mainboard/protectli/vault_cml: Switch to IT8784E ...................................................................... mainboard/protectli/vault_cml: Switch to IT8784E The first platform samples came with IT8786E. The production units switched to IT8784E in the final design. Change the code to use IT8784E and reflect the proprietary firmware configuration of the SIO chip. TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the configuration with superiotool and compare the configuration with proprietary firmware. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e --- M src/mainboard/protectli/vault_cml/Kconfig M src/mainboard/protectli/vault_cml/acpi/superio.asl M src/mainboard/protectli/vault_cml/bootblock.c M src/mainboard/protectli/vault_cml/devicetree.cb M src/mainboard/protectli/vault_cml/dsdt.asl 5 files changed, 50 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74175/1 diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 6e7136d..fa66063 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -17,7 +17,7 @@ select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPI_FLASH_MACRONIX - select SUPERIO_ITE_IT8786E + select SUPERIO_ITE_IT8784E config MAINBOARD_DIR default "protectli/vault_cml" diff --git a/src/mainboard/protectli/vault_cml/acpi/superio.asl b/src/mainboard/protectli/vault_cml/acpi/superio.asl index 853b087..f5c9191 100644 --- a/src/mainboard/protectli/vault_cml/acpi/superio.asl +++ b/src/mainboard/protectli/vault_cml/acpi/superio.asl @@ -1 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8784E_SHOW_UARTA +#undef IT8784E_SHOW_UARTB +#undef IT8784E_SHOW_EC +#undef IT8784E_SHOW_KBC +#undef IT8784E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8784E_SHOW_SP1 +#define IT8784E_SHOW_EC +#include <superio/ite/it8784e/acpi/superio.asl> diff --git a/src/mainboard/protectli/vault_cml/bootblock.c b/src/mainboard/protectli/vault_cml/bootblock.c index 9052fb8..82c46f9 100644 --- a/src/mainboard/protectli/vault_cml/bootblock.c +++ b/src/mainboard/protectli/vault_cml/bootblock.c @@ -3,18 +3,18 @@ #include <bootblock_common.h> #include <soc/gpio.h> #include <superio/ite/common/ite.h> -#include <superio/ite/it8786e/it8786e.h> +#include <superio/ite/it8784e/it8784e.h> #include "gpio.h" -#define UART_DEV PNP_DEV(0x2e, IT8786E_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8784E_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8784E_GPIO) void bootblock_mainboard_early_init(void) { /* CLKIN freq 24MHz, Ext CLKIN for Watchdog, Internal VCC_OK */ ite_reg_write(GPIO_DEV, 0x23, 0x49); /* Set pin native functions */ - ite_reg_write(GPIO_DEV, 0x26, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xf3); /* Set GPIOS exposed on pin header as GPIO functions */ ite_reg_write(GPIO_DEV, 0x29, 0xc0); /* External CLKIN PCICLK */ diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 154d81a..3ba2b01 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -192,17 +192,17 @@ device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on - chip superio/ite/it8786e - register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "0x63" + chip superio/ite/it8784e + register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_MODE_DISABLED" - register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" + register "TMPIN3.mode" = "THERMAL_PECI" + register "TMPIN3.offset" = "0x63" register "ec.vin_mask" = "VIN_ALL" register "ec.smbus_24mhz" = "1" register "ec.smbus_en" = "1" # FAN1 is CPU fan (connector on board) register "FAN1.mode" = "FAN_SMART_AUTOMATIC" - register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmpin" = " 3" register "FAN1.smart.tmp_off" = "40" register "FAN1.smart.tmp_start" = "60" register "FAN1.smart.tmp_full" = "85" @@ -215,24 +215,18 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on # COM 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end + device pnp 2e.2 on end # COM 2 device pnp 2e.3 off end # Printer Port device pnp 2e.4 on # Environment Controller io 0x60 = 0xa40 io 0x62 = 0xa30 irq 0x70 = 9 + irq 0xf0 = 0x80 # clear 3VSB status end device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # COM 3 - device pnp 2e.9 off end # COM 4 device pnp 2e.a off end # CIR - device pnp 2e.b off end # COM 5 - device pnp 2e.c off end # COM 6 end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/protectli/vault_cml/dsdt.asl b/src/mainboard/protectli/vault_cml/dsdt.asl index cb0922a..8240fc9 100644 --- a/src/mainboard/protectli/vault_cml/dsdt.asl +++ b/src/mainboard/protectli/vault_cml/dsdt.asl @@ -21,5 +21,10 @@ #include <soc/intel/cannonlake/acpi/southbridge.asl> } + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + #include <southbridge/intel/common/acpi/sleepstates.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/74175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e Gerrit-Change-Number: 74175 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: superio/ite: Add IT8784E support
by Michał Żygowski (Code Review) 03 Apr '23

03 Apr '23

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74174 ) Change subject: superio/ite: Add IT8784E support ...................................................................... superio/ite: Add IT8784E support IT8784E is basically a IT8786E stripped from serial ports 3-6. The patch creates a chip directory for IT8784E used by protectli/vault_cml platforms. TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the configuration with superiotool and compare the configuration with proprietary firmware. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e --- M src/superio/ite/Makefile.inc A src/superio/ite/it8784e/Kconfig A src/superio/ite/it8784e/Makefile.inc A src/superio/ite/it8784e/acpi/superio.asl A src/superio/ite/it8784e/chip.h A src/superio/ite/it8784e/it8784e.h A src/superio/ite/it8784e/superio.c 7 files changed, 299 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/74174/1 diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 8ff122b..23d86da 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -17,4 +17,5 @@ subdirs-y += it8728f subdirs-y += it8772f subdirs-y += it8783ef +subdirs-y += it8784e subdirs-y += it8786e diff --git a/src/superio/ite/it8784e/Kconfig b/src/superio/ite/it8784e/Kconfig new file mode 100644 index 0000000..66dd6c9 --- /dev/null +++ b/src/superio/ite/it8784e/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_ITE_IT8784E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN diff --git a/src/superio/ite/it8784e/Makefile.inc b/src/superio/ite/it8784e/Makefile.inc new file mode 100644 index 0000000..2a3a6d9 --- /dev/null +++ b/src/superio/ite/it8784e/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_ITE_IT8784E) += superio.c diff --git a/src/superio/ite/it8784e/acpi/superio.asl b/src/superio/ite/it8784e/acpi/superio.asl new file mode 100644 index 0000000..7d064dd --- /dev/null +++ b/src/superio/ite/it8784e/acpi/superio.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8784E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, untested + * 0x2 UARTB Implemented, untested + * 0x3 PP Not implemented + * 0x4 EC Implemented, untested + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Not implemented + * 0xa CIR Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8784E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8784E_SHOW_UARTB If defined, UARTB will be exposed. + * IT8784E_SHOW_KBC If defined, the KBC will be exposed. + * IT8784E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * IT8784E_SHOW_EC If defined, EC will be exposed. + */ + + #undef SUPERIO_CHIP_NAME + #define SUPERIO_CHIP_NAME IT8784E + #include <superio/acpi/pnp.asl> + + #undef PNP_DEFAULT_PSC + #define PNP_DEFAULT_PSC Return (0) /* no power management */ + + #define CONFIGURE_CONTROL CCTL + + Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8784E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 + #if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 + #else + #define PNP_ENTER_MAGIC_4TH 0xaa + #endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include <superio/acpi/pnp_config.asl> + + #ifdef IT8784E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include <superio/acpi/pnp_uart.asl> + #endif + + #ifdef IT8784E_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> + #endif + + #ifdef IT8784E_SHOW_EC + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 4 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x04 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> + #endif + + #ifdef IT8784E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #ifdef IT8784E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 + #endif + #include <superio/acpi/pnp_kbc.asl> + #endif + } + \ No newline at end of file diff --git a/src/superio/ite/it8784e/chip.h b/src/superio/ite/it8784e/chip.h new file mode 100644 index 0000000..475f9c4 --- /dev/null +++ b/src/superio/ite/it8784e/chip.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8784E_CHIP_H +#define SUPERIO_ITE_IT8784E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8784e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8784E_CHIP_H */ diff --git a/src/superio/ite/it8784e/it8784e.h b/src/superio/ite/it8784e/it8784e.h new file mode 100644 index 0000000..6b819fd --- /dev/null +++ b/src/superio/ite/it8784e/it8784e.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_ITE_IT8784E_H +#define SUPERIO_ITE_IT8784E_H + +#define IT8784E_SP1 0x01 /* COM1 */ +#define IT8784E_SP2 0x02 /* COM2 */ +#define IT8784E_PP 0x03 /* Printer port */ +#define IT8784E_EC 0x04 /* Environment controller */ +#define IT8784E_KBCK 0x05 /* Keyboard */ +#define IT8784E_KBCM 0x06 /* Mouse */ +#define IT8784E_GPIO 0x07 /* GPIO */ +#define IT8784E_CIR 0x0a /* Consumer IR */ + +#endif /* SUPERIO_ITE_IT8784E_H */ diff --git a/src/superio/ite/it8784e/superio.c b/src/superio/ite/it8784e/superio.c new file mode 100644 index 0000000..85fc42e --- /dev/null +++ b/src/superio/ite/it8784e/superio.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "it8784e.h" +#include "chip.h" + +static void it8784e_init(struct device *const dev) +{ + const struct superio_ite_it8784e_config *conf; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8784E_EC: + conf = dev->chip_info; + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8784E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8784e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8784E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 2 */ + { NULL, IT8784E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Printer Port */ + { NULL, IT8784E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | + PNP_MSC0, + 0x0ff8, 0x0ffc, }, + /* Environmental Controller */ + { NULL, IT8784E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | + PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | + PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB | + PNP_MSCC, + 0x0ff8, 0x0ffc, }, + /* KBC Keyboard */ + { NULL, IT8784E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8784E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8784E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | + PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | + PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | + PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, + 0x0ffc, 0x0fff, }, + /* Consumer Infrared */ + { NULL, IT8784E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8784e_ops = { + CHIP_NAME("ITE IT8784E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/74174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e Gerrit-Change-Number: 74174 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/common: Add code to order the different types of cores
by Paul Menzel (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Subrata Banik, Sridhar Siricilla, Kyösti Mälkki, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72132 ) Change subject: soc/intel/common: Add code to order the different types of cores ...................................................................... Patch Set 15: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72132/comment/b08af3b9_b0cee4d0 PS15, Line 7: Add code to Redundant as patches are about code. https://review.coreboot.org/c/coreboot/+/72132/comment/8e6a9418_65f5d3db PS15, Line 11: for c in {0..7}; Please add a blank line above. https://review.coreboot.org/c/coreboot/+/72132/comment/90b41501_0078acc1 PS15, Line 11: for c in {0..7}; : do : cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list; : done Shorter: $ grep . /sys/devices/system/cpu/cpu*/topology/thread_siblings_list https://review.coreboot.org/c/coreboot/+/72132/comment/f1428c1d_cdd22d31 PS15, Line 11: for c in {0..7}; : do : cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list; : done : 0-1 : 4 : 5 : 6 : 7 : 0-1 : 2-3 : 2-3 You could use Markdown formatting, and indent code blocks by four spaces. https://review.coreboot.org/c/coreboot/+/72132/comment/a2fab999_68f34663 PS15, Line 24: Existing code presents mix of different cores to OS and causes CPU load : balancing and power/performance impact. Why? What ordering does the OS require? Maybe reference the kernel source code. -- To view, visit https://review.coreboot.org/c/coreboot/+/72132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Gerrit-Change-Number: 72132 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:08:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74168 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS ...................................................................... soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS The Intel FSP used on ChromeOS platform has dropped the `CpuFeaturesPei.ffs` module to opt for coreboot running this additional feature programming on BSP and APs. TEST=Able to build and boot google/rex without any boot regression. Please refer to the boot time and SPI flash savings after dropping the FSP feature programming: Boot time savings=10ms SPI Flash size savings=34KB Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74168/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Gerrit-Change-Number: 74168 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74168 ) Change subject: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74168/comment/e7bfcc29_8ceb3ab8 PS1, Line 12: > > Please describe the problem, and document size and time savings. > > choosing anything over FSP is also desirable and if you are interest to know the problem statement, please refer to https://blog.osfw.foundation/osf-intel-reduce-fsp-boundary/ > > I don't think, we have some mandatory rule to write the problem statement in such details. If anyone would like to understand the problem statement then source of the selected kconfig should be enough. > > I have added time and benefit anyway, please feel free to open this -- To view, visit https://review.coreboot.org/c/coreboot/+/74168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Gerrit-Change-Number: 74168 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:02:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74168 ) Change subject: soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74168/comment/2b91ca32_ed71dde9 PS1, Line 10: those > this Ack https://review.coreboot.org/c/coreboot/+/74168/comment/e4df6aa7_b4c2c179 PS1, Line 12: > Please describe the problem, and document size and time savings. choosing anything over FSP is also desirable and if you are interest to know the problem statement, please refer to https://blog.osfw.foundation/osf-intel-reduce-fsp-boundary/ I don't think, we have some mandatory rule to write the problem statement in such details. If anyone would like to understand the problem statement then source of the selected kconfig should be enough. I have added time and benefit anyway, -- To view, visit https://review.coreboot.org/c/coreboot/+/74168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de Gerrit-Change-Number: 74168 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 13:00:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74161 to look at the new patch set (#4). Change subject: soc/intel/meteorlake: Enable VMX using coreboot CPU feature program ...................................................................... soc/intel/meteorlake: Enable VMX using coreboot CPU feature program This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization if not done by FSP (based on DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake SoC based platform. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/cpu.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74161/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Enable VMX
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74161 ) Change subject: soc/intel/meteorlake: Enable VMX ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74161/comment/a01cce33_73c62853 PS3, Line 7: soc/intel/meteorlake: Enable VMX > Yes, reading the commit messages of all the change-sets, it’s clear. […] Ack https://review.coreboot.org/c/coreboot/+/74161/comment/d4529ba9_23a9e6ea PS3, Line 9: This function calls into `set_feature_ctrl_vmx_arg()` : to enable VMX for virtualization. > This should also be elaborated. Ack File src/soc/intel/meteorlake/cpu.c: https://review.coreboot.org/c/coreboot/+/74161/comment/1bf1c4fa_d3ee62cf PS3, Line 149: Vmx > VMX Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Gerrit-Change-Number: 74161 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Allow to drop redundant CPU feature programming
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Hello build bot (Jenkins), Tarun Tuli, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74167 to look at the new patch set (#2). Change subject: soc/intel/meteorlake: Allow to drop redundant CPU feature programming ...................................................................... soc/intel/meteorlake: Allow to drop redundant CPU feature programming This patch introduces a new config named `DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU feature programming on BSP and on APs using the "CpuFeaturesPei.efi" module. Most of this feature programming is getting performed today in scope of coreboot doing MP Init. Running this redundant programming in scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) results in CPU exception (for example: attempting to reprogram CPU feature lock MSR is causing CPU exception). SoC users should select this config after dropping "CpuFeaturesPei.ffs" module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional feature programming on BSP and APs. This feature is by default enabled, in case of "coreboot running MP init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected. At present, this option does not do anything unless any platform eventually decides to drop FSP feature programming module and choose coreboot CPU feature programming over it. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/74167/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Gerrit-Change-Number: 74167 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Option to drop redundant CPU feature programming
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74167 ) Change subject: soc/intel/meteorlake: Option to drop redundant CPU feature programming ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Add comment, that this option does not do anything yet. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Gerrit-Change-Number: 74167 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:51:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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