coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/meteorlake: Option to drop redundant CPU feature programming
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Kapil Porwal, Ivy Jian, Eric Lai, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74167 ) Change subject: soc/intel/meteorlake: Option to drop redundant CPU feature programming ...................................................................... Patch Set 1: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74167/comment/88f93c55_ec6a0552 PS1, Line 7: Option to drop redundant CPU feature programming > “Allow to …” or “Add option to …”. Ack https://review.coreboot.org/c/coreboot/+/74167/comment/e16dadbd_7132c81d PS1, Line 14: these featureprogramming are > this feature programming is Ack https://review.coreboot.org/c/coreboot/+/74167/comment/4578548a_342fb3d9 PS1, Line 15: these > this Ack https://review.coreboot.org/c/coreboot/+/74167/comment/06434355_36748328 PS1, Line 17: would results > results Ack https://review.coreboot.org/c/coreboot/+/74167/comment/b9215d11_53bcce5c PS1, Line 17: in CPU exception > Give an example? Ack https://review.coreboot.org/c/coreboot/+/74167/comment/a5fedf83_c301e107 PS1, Line 19: to > should Ack https://review.coreboot.org/c/coreboot/+/74167/comment/5977c7dc_7fc7e295 PS1, Line 23: default > by default Ack https://review.coreboot.org/c/coreboot/+/74167/comment/9be0d089_f708f0b3 PS1, Line 25: > Can’t coreboot detect if that firmware volume is present? I wish! -- To view, visit https://review.coreboot.org/c/coreboot/+/74167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Gerrit-Change-Number: 74167 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:49:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Add code to order the different types of cores
by Jan Samek (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Subrata Banik, Sridhar Siricilla, Kyösti Mälkki, Elyes Haouas. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72132 ) Change subject: soc/intel/common: Add code to order the different types of cores ...................................................................... Patch Set 15: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72132/comment/4610e8ae_0a007df0 PS14, Line 39: comptue > compute Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Gerrit-Change-Number: 72132 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:39:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Add code to order the different types of cores
by Sridhar Siricilla (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Subrata Banik, Sridhar Siricilla, Kyösti Mälkki, Elyes Haouas. Hello build bot (Jenkins), Subrata Banik, Ronak Kanabar, Sukumar Ghorai, Kyösti Mälkki, Elyes Haouas, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72132 to look at the new patch set (#15). Change subject: soc/intel/common: Add code to order the different types of cores ...................................................................... soc/intel/common: Add code to order the different types of cores Currently coreboot presents the BSP core first, then efficient cores and Performance cores as indicated below: for c in {0..7}; do cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list; done 0-1 4 5 6 7 0-1 2-3 2-3 Existing code presents mix of different cores to OS and causes CPU load balancing and power/performance impact. So, the patch fixes this disorder by ordering the Performance cores first, compute die efficient cores next, and finally SOC efficient cores if they are present. BUG=b:262886449 TEST=Verified the code on Rex system After the fix: for c in {0..7}; do cat /sys/devices/system/cpu/cpu$c/topology/thread_siblings_list; done 0-1 0-1 2-3 2-3 4 5 6 7 Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 3 files changed, 88 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/72132/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/72132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Gerrit-Change-Number: 72132 Gerrit-PatchSet: 15 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: src/arch/ Fixed some linter warnings and errors
by build bot (Jenkins) (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Philipp Hug, Julius Werner, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74173 ) Change subject: src/arch/ Fixed some linter warnings and errors ...................................................................... Patch Set 1: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172926): https://review.coreboot.org/c/coreboot/+/74173/comment/3961eb3a_d1f0528e PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172926): https://review.coreboot.org/c/coreboot/+/74173/comment/021773db_b1be4d0b PS1, Line 9: This is my first commit to coreboot, so please tell me if I'm missing something. Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-172926): https://review.coreboot.org/c/coreboot/+/74173/comment/26b19b5b_7e185003 PS1, Line 10: I corrected some linter issues, deleting whitespaces, correcting identations etc. Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I976cffe971695f591ec42fce46e6743444277759 Gerrit-Change-Number: 74173 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp M Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:23:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/arch/ Fixed some linter warnings and errors
by Philipp M (Code Review) 03 Apr '23

03 Apr '23

Philipp M has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74173 ) Change subject: src/arch/ Fixed some linter warnings and errors ...................................................................... src/arch/ Fixed some linter warnings and errors This is my first commit to coreboot, so please tell me if I'm missing something. I corrected some linter issues, deleting whitespaces, correcting identations etc. Some changes seemed like no big addition to readability to me, but I guess having everything more uniform is good. Signed-off-by: Philipp Macher <philipp-macher(a)web.de> Change-Id: I976cffe971695f591ec42fce46e6743444277759 --- M src/arch/arm/include/arch/hlt.h M src/arch/arm/include/armv7/arch/cache.h M src/arch/arm64/include/arch/hlt.h M src/arch/riscv/include/mcall.h M src/arch/riscv/trap_handler.c M src/console/vtxprintf.c 6 files changed, 68 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74173/1 diff --git a/src/arch/arm/include/arch/hlt.h b/src/arch/arm/include/arch/hlt.h index 7229643..7bdae39 100644 --- a/src/arch/arm/include/arch/hlt.h +++ b/src/arch/arm/include/arch/hlt.h @@ -5,7 +5,8 @@ static __always_inline void hlt(void) { - for (;;) ; + for (;;) + ; } #endif /* ARCH_HLT_H */ diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index f10b8a0..1507df7 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -234,7 +234,7 @@ * Note: L2CTLR can only be written when the L2 memory system * is idle, ie before the MMU is enabled. */ - asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" ); + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); isb(); } @@ -249,7 +249,7 @@ /* write L2 Auxiliary Control Register (L2ACTLR) */ static inline void write_l2actlr(uint32_t val) { - asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); + asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory"); isb(); } diff --git a/src/arch/arm64/include/arch/hlt.h b/src/arch/arm64/include/arch/hlt.h index 7229643..7bdae39 100644 --- a/src/arch/arm64/include/arch/hlt.h +++ b/src/arch/arm64/include/arch/hlt.h @@ -5,7 +5,8 @@ static __always_inline void hlt(void) { - for (;;) ; + for (;;) + ; } #endif /* ARCH_HLT_H */ diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 803ee3e..7e56eac 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -57,11 +57,11 @@ #define MACHINE_STACK_TOP() ({ \ /* coverity[uninit_use] : FALSE */ \ register uintptr_t sp asm ("sp"); \ - (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) + (void *)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) // hart-local storage, at top of stack -#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) +#define HLS() ((hls_t *)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((hls_t *)((void *)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) #define MACHINE_STACK_SIZE RISCV_PGSIZE diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f5953d3..7d6e394 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -33,10 +33,10 @@ static const char *mstatus_to_previous_mode(uintptr_t ms) { switch (ms & MSTATUS_MPP) { - case 0x00000000: return "user"; - case 0x00000800: return "supervisor"; - case 0x00001000: return "hypervisor"; - case 0x00001800: return "machine"; + case 0x00000000: return "user"; + case 0x00000800: return "supervisor"; + case 0x00001000: return "hypervisor"; + case 0x00001800: return "machine"; } return "unknown"; @@ -61,7 +61,7 @@ previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id); printk(BIOS_DEBUG, "Previous mode: %s%s\n", - previous_mode, mprv? " (MPRV)":""); + previous_mode, mprv ? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); printk(BIOS_DEBUG, "Stored ra: %p\n", (void *)tf->gpr[1]); @@ -117,31 +117,31 @@ } switch (tf->cause) { - case CAUSE_MISALIGNED_FETCH: - case CAUSE_FETCH_ACCESS: - case CAUSE_ILLEGAL_INSTRUCTION: - case CAUSE_BREAKPOINT: - case CAUSE_LOAD_ACCESS: - case CAUSE_STORE_ACCESS: - case CAUSE_USER_ECALL: - case CAUSE_HYPERVISOR_ECALL: - case CAUSE_MACHINE_ECALL: - print_trap_information(tf); - break; - case CAUSE_SUPERVISOR_ECALL: - handle_sbi(tf); - return; - case CAUSE_MISALIGNED_LOAD: - case CAUSE_MISALIGNED_STORE: - print_trap_information(tf); - handle_misaligned(tf); - return; - default: - printk(BIOS_EMERG, "================================\n"); - printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); - printk(BIOS_EMERG, "================================\n"); - print_trap_information(tf); - break; + case CAUSE_MISALIGNED_FETCH: + case CAUSE_FETCH_ACCESS: + case CAUSE_ILLEGAL_INSTRUCTION: + case CAUSE_BREAKPOINT: + case CAUSE_LOAD_ACCESS: + case CAUSE_STORE_ACCESS: + case CAUSE_USER_ECALL: + case CAUSE_HYPERVISOR_ECALL: + case CAUSE_MACHINE_ECALL: + print_trap_information(tf); + break; + case CAUSE_SUPERVISOR_ECALL: + handle_sbi(tf); + return; + case CAUSE_MISALIGNED_LOAD: + case CAUSE_MISALIGNED_STORE: + print_trap_information(tf); + handle_misaligned(tf); + return; + default: + printk(BIOS_EMERG, "================================\n"); + printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); + printk(BIOS_EMERG, "================================\n"); + print_trap_information(tf); + break; } die("Can't recover from trap. Halting.\n"); diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index cfba6db..0de657e 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -127,11 +127,21 @@ repeat: ++fmt; /* this also skips first '%' */ switch (*fmt) { - case '-': flags |= LEFT; goto repeat; - case '+': flags |= PLUS; goto repeat; - case ' ': flags |= SPACE; goto repeat; - case '#': flags |= SPECIAL; goto repeat; - case '0': flags |= ZEROPAD; goto repeat; + case '-': + flags |= LEFT; + goto repeat; + case '+': + flags |= PLUS; + goto repeat; + case ' ': + flags |= SPACE; + goto repeat; + case '#': + flags |= SPECIAL; + goto repeat; + case '0': + flags |= ZEROPAD; + goto repeat; } /* get field width */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I976cffe971695f591ec42fce46e6743444277759 Gerrit-Change-Number: 74173 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp M Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Enable CSE pre-cpu timestamps
by Kapil Porwal (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73759 ) Change subject: mb/google/rex: Enable CSE pre-cpu timestamps ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Gerrit-Change-Number: 73759 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:16:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable CSE pre-cpu timestamps
by Subrata Banik (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73759 ) Change subject: mb/google/rex: Enable CSE pre-cpu timestamps ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Patchset: PS9: we will land this after CSE uprev. -- To view, visit https://review.coreboot.org/c/coreboot/+/73759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Gerrit-Change-Number: 73759 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:15:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
by Kapil Porwal (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73713 ) Change subject: soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Gerrit-Change-Number: 73713 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:15:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib: Add new "DMU load completed" TS
by Kapil Porwal (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74047 ) Change subject: commonlib: Add new "DMU load completed" TS ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d2da820f39c40ea864d15d25a94a68497b2af3d Gerrit-Change-Number: 74047 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:15:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/alderlake: Add support for CSE timestamp data versions
by Kapil Porwal (Code Review) 03 Apr '23

03 Apr '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Wonkyu Kim. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73712 ) Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Gerrit-Change-Number: 73712 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Apr 2023 12:14:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2023