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Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Patch Set 2:
(1 comment)
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/74150/comment/2669116d_7aa5b538
PS1, Line 117: $(call add-special-class,all_x86)
: all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2)))
> ha, that solved the problem. […]
welcome :)
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Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Patch Set 2:
(1 comment)
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/74150/comment/249018a3_78346571
PS1, Line 117: $(call add-special-class,all_x86)
: all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2)))
> moved this above the verstage_86 expansion; let's see if jenkins now like the next patches better
ha, that solved the problem. thanks for looking into this
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Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions
......................................................................
Patch Set 8: Code-Review+2
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Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions
......................................................................
Patch Set 8:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73712/comment/d49081e2_5b5cf3ef
PS7, Line 10: Alderlake/Raptorlake
> Alder Lake/Raptor Lake
Done
https://review.coreboot.org/c/coreboot/+/73712/comment/b16c4755_677cc7c6
PS7, Line 10: Meteorlake
> Meteor Lake
Done
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/73712/comment/8ebbd2e7_9e1aab9d
PS7, Line 200: ADL and RPL
> I’d spell it out.
Done
https://review.coreboot.org/c/coreboot/+/73712/comment/caaa344c_b4035f98
PS7, Line 207: MTL-M/P
> Ditto.
Done
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Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kapil Porwal, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73712
to look at the new patch set (#8).
Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions
......................................................................
soc/intel/alderlake: Add support for CSE timestamp data versions
CSE performance data timestamps are different for version 1
Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch
moves the current ADL/RPL timestamp definitions to a separate
header file. It marks current structure as version 1.
BUG=b:259366109
TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.
Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
---
M src/mainboard/google/brya/Kconfig
M src/soc/intel/alderlake/Makefile.inc
A src/soc/intel/alderlake/cse_telemetry.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/telemetry.c
M src/soc/intel/common/block/include/intelblocks/cse.h
A src/soc/intel/common/block/include/intelblocks/cse_telemetry.h
A src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h
8 files changed, 197 insertions(+), 127 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/73712/8
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74176 )
Change subject: payloads/edk2: Set max variable size to 0x8000 for SMMSTORE
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Why not squash it into the SMMSTORE patch? I'm starting to use: […]
There are about 20 versions of the SMMSTORE patch that are used by different people
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Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74150/comment/7dd91a1a_2e9ffe3e
PS1, Line 14: verstage_x8
> nit: verstage_x86
Done
https://review.coreboot.org/c/coreboot/+/74150/comment/f3792708_36ba833b
PS1, Line 19: per
> nit: pre-Zen?
Done
Patchset:
PS1:
> CB:74152 uses this in src/cpu where the verstage_x86 target and the other stage targets were used. […]
i'll try to look into using all_x86 in arch/x86 and cpu/x86. might be useful to use that instead of the all in all makefiles in those two directories
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/74150/comment/4f107513_3a1a9d98
PS1, Line 117: $(call add-special-class,all_x86)
: all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2)))
> looks like this needs to go above the expansion for verstage_x86 above
moved this above the verstage_86 expansion; let's see if jenkins now like the next patches better
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Hello build bot (Jenkins), Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74150
to look at the new patch set (#2).
Change subject: Makefile.inc: introduce all_x86 target
......................................................................
Makefile.inc: introduce all_x86 target
For compilation units that should be built for all stages that run on
the x86 cores in a newer AMD SoC, but can't be built for verstage on PSP
which is an ARM core, the all target can't be used, since that would
result in the compilation unit also being added to the verstage target
in the verstage on PSP case. In order to not need to add a compilation
unit to bootblock, verstage_x88, romstage and ramstage in separate lines
in the makefile, introduce the all_x86 target that adds a file to
bootblock, verstage_x86, romstage, postcar, ramstage. The compilation
units also need to be added to the postcar stage which is only present
on the pre-Zen SoCs to be able to also use the all_x86 target in common
AMD code that is also used in those pre-Zen SoCs.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9d0184182b931185990094d0874b49c0b5cb9f7e
---
M Makefile.inc
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74150/2
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