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Change subject: soc/intel: Don't report _S1 state when unsupported
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/pmc/Kconfig:
https://review.coreboot.org/c/coreboot/+/74760/comment/3ebdd370_68f056ce
PS7, Line 7: select ACPI_S1_NOT_SUPPORTED
can we move this at line #5 ?
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Change subject: cpu/x86/entry16.S: Move reset vector to this file
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Patch Set 2: Code-Review+1
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74800
to look at the new patch set (#2).
Change subject: cpu/x86/entry16.S: Move reset vector to this file
......................................................................
cpu/x86/entry16.S: Move reset vector to this file
This makes the code easier to follow.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I5a4b7fe99875a1addf611f569990ff9a3beda3ba
---
M src/cpu/x86/Makefile.inc
M src/cpu/x86/entry16.S
D src/cpu/x86/reset16.S
3 files changed, 18 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/74800/2
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Change subject: cpu/x86/entry16.S: Move reset vector to this file
......................................................................
Patch Set 1:
(2 comments)
File src/cpu/x86/entry16.S:
https://review.coreboot.org/c/coreboot/+/74800/comment/1947cba3_571b66fb
PS1, Line 155: /* This is the first instruction the CPU runs when coming out of reset. */
: .section ".reset", "ax", %progbits
: .globl _start
> alignment
Done
https://review.coreboot.org/c/coreboot/+/74800/comment/14384e95_ac007ec3
PS1, Line 159:
> maybe tab?
Done
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Change subject: mb/google/rex/var/screebo: Add initial setup for gpio config
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Patch Set 7: Code-Review+2
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Change subject: mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIG
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74775/comment/94bd20a9_487890dd
PS1, Line 13: 2
> 1?
mostly this is in preparation of proto 2 sku
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Change subject: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V
......................................................................
Patch Set 1:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74799/comment/ff7b38f5_1f78d450
PS1, Line 2: weidongwd
Please configure your full name:
$ git config --global user.name "…"
$ git commit --amend --author="… <…>" -s
https://review.coreboot.org/c/coreboot/+/74799/comment/a10087ba_c140bf22
PS1, Line 7: supports
support
https://review.coreboot.org/c/coreboot/+/74799/comment/2c590303_8edaa59c
PS1, Line 8:
> Possible unwrapped commit description (prefer a maximum 72 chars per line)
Please fix.
https://review.coreboot.org/c/coreboot/+/74799/comment/780b2483_691b0b16
PS1, Line 9: Adapts ACPI and SMBIOS related codes for RISC-V, and then passes their addresses to the OS via FDT.
Please use imperative mood (present):
> Adapt ACPI and SMBIOS related code for RISC-V, and then pass their addresses to the OS via FDT.
https://review.coreboot.org/c/coreboot/+/74799/comment/50d399cb_1c122e5e
PS1, Line 10:
I guess you should also elaborate a little more on the implementation. What is the difference to x86 for example.
https://review.coreboot.org/c/coreboot/+/74799/comment/0bac2a42_af90dbf7
PS1, Line 10:
Please add a TEST= tag.
https://review.coreboot.org/c/coreboot/+/74799/comment/b3997047_464280b0
PS1, Line 11: weidongwd
Ditto.
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