coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
by Karthik Ramasubramanian (Code Review) 27 Apr '23

27 Apr '23

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74742 ) Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern ...................................................................... Patch Set 2: (1 comment) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/74742/comment/61c13aa0_eb671ac7 PS2, Line 1010: match.rm_so + 1; > Why do we move the cursor to match.rm_so + 1 instead of match.rm_eo? […] … [View More]

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/craask: avoid camera LED blinking during boot
by Eric Lai (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Jimmy Su, Paul Menzel, Reka Norman, Tyler Wang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74728 ) Change subject: mb/google/nissa/var/craask: avoid camera LED blinking during boot ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS1: > Hi Eric & Tyler, […] I see. thanks for explanation. -- To view, visit https:/… [View More]

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/craask: avoid camera LED blinking during boot
by Jimmy Su (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Paul Menzel, Reka Norman, Tyler Wang, Eric Lai. Jimmy Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74728 ) Change subject: mb/google/nissa/var/craask: avoid camera LED blinking during boot ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74728/comment/caa6b99e_d0019870 PS1, Line 9: , &… [View More]

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/craask: avoid camera LED blinking during boot
by Jimmy Su (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Reka Norman, Tyler Wang, Eric Lai. Hello build bot (Jenkins), Tarun Tuli, Reka Norman, Tyler Wang, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74728 to look at the new patch set (#2). Change subject: mb/google/nissa/var/craask: avoid camera LED blinking during boot ...................................................................... mb/google/nissa/var/craask: avoid camera LED … [View More]

1 0

[S] Change in coreboot[master]: mb/google/nissa/var/craask: avoid camera LED blinking during boot
by Jimmy Su (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Reka Norman, Tyler Wang, Eric Lai. Jimmy Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74728 ) Change subject: mb/google/nissa/var/craask: avoid camera LED blinking during boot ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Hi Jimmy, […] Hi Eric & Tyler, If you remove D15 in VCM configuration, you will meet some I2C error during … [View More]

1 0

[M] Change in coreboot[master]: mb/google/brya: Create gothrax variant
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74748 ) Change subject: mb/google/brya: Create gothrax variant ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175072): https://review.coreboot.org/c/… [View More]

1 0

[M] Change in coreboot[master]: mb/google/brya: Create gothrax variant
by Yunlong Jia (Code Review) 27 Apr '23

27 Apr '23

Yunlong Jia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74748 ) Change subject: mb/google/brya: Create gothrax variant ...................................................................... mb/google/brya: Create gothrax variant Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=279614675 BRANCH=None TEST=util/… [View More]abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/gothrax/include/variant/ec.h A src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h A src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc A src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/gothrax/overridetree.cb 8 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/74748/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index eb1790e..fc22168 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -237,6 +237,7 @@ default "Hades" if BOARD_GOOGLE_HADES default "Uldren" if BOARD_GOOGLE_ULDREN default "Yavilla" if BOARD_GOOGLE_YAVILLA + default "Gothrax" if BOARD_GOOGLE_GOTHRAX config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -284,6 +285,7 @@ default "hades" if BOARD_GOOGLE_HADES default "uldren" if BOARD_GOOGLE_ULDREN default "yavilla" if BOARD_GOOGLE_YAVILLA + default "gothrax" if BOARD_GOOGLE_GOTHRAX config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 9cdc8e7..e9f1003 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -374,3 +374,7 @@ select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE + +config BOARD_GOOGLE_GOTHRAX + bool "-> Gothrax" + select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h b/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h b/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/74748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Gerrit-Change-Number: 74748 Gerrit-PatchSet: 1 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange [View Less]

1 0

[M] Change in coreboot[master]: ACPI: Make FADT entries for SMI architectural
by Kyösti Mälkki (Code Review) 27 Apr '23

27 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74600 ) Change subject: ACPI: Make FADT entries for SMI architectural ...................................................................... ACPI: Make FADT entries for SMI architectural Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600 Reviewed-by: Arthur Heymans <arthur(a)… [View More]aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/arch/x86/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/braswell/fadt.c M src/soc/intel/broadwell/pch/fadt.c M src/soc/intel/common/block/acpi/acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 20 files changed, 21 insertions(+), 98 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 0ff0ded..e1ef978 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <cf9_reset.h> +#include <cpu/x86/smm.h> void arch_fill_fadt(acpi_fadt_t *fadt) { @@ -17,4 +18,10 @@ fadt->flags |= ACPI_FADT_RESET_REGISTER; } + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + } } diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 3482bbb..07cdcbf 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -38,12 +38,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index d961fcf..df86296 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -40,12 +40,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index fddc892..7e703c0 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -39,12 +39,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index d067deb..09d7b8b 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -40,12 +40,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a5df99d..366751f 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -43,11 +43,6 @@ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 7be76c1..b3895b3 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -39,11 +39,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index c01a79a..8a2831b 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -10,11 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index d071b92..526f797 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,11 +11,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/soc/intel/broadwell/pch/fadt.c index 2ffebc3..9a4c036 100644 --- a/src/soc/intel/broadwell/pch/fadt.c +++ b/src/soc/intel/broadwell/pch/fadt.c @@ -10,11 +10,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index fda82d4..9722881 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -94,11 +94,6 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index fe65fb2..dfe9986 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -25,11 +25,6 @@ { printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE); - if (permanent_smi_handler()) { - fadt->smi_cmd = ACPI_SMI_CTL_PORT; - fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; - fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index 31f2a06..e76682d 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -12,11 +12,6 @@ struct southbridge_intel_bd82x6x_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 66ae2bb..00e204e 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -16,10 +16,6 @@ */ void acpi_fill_fadt(acpi_fadt_t *fadt) { - if (permanent_smi_handler()) { - /* TODO: SMI handler is not implemented. */ - fadt->smi_cmd = 0x00; - } fadt->pm1a_evt_blk = DEFAULT_PMBASE; fadt->pm1a_cnt_blk = DEFAULT_PMBASE + PMCNTRL; diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index 5015659..e5ad336 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -8,11 +8,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + 0x4; diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 7cdd631..ccbc504 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -13,11 +13,6 @@ struct southbridge_intel_i82801gx_config *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c index 92fece2..bcd7d90 100644 --- a/src/southbridge/intel/i82801ix/fadt.c +++ b/src/southbridge/intel/i82801ix/fadt.c @@ -9,11 +9,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c index a2defd2..73d7ea0 100644 --- a/src/southbridge/intel/i82801jx/fadt.c +++ b/src/southbridge/intel/i82801jx/fadt.c @@ -9,11 +9,6 @@ { u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index a917fb8..d750890 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -12,11 +12,6 @@ struct southbridge_intel_ibexpeak_config *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index ee7b309..eaea091 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -12,11 +12,6 @@ struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; u16 pmbase = get_pmbase(); - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - } fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/74600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349 Gerrit-Change-Number: 74600 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

1 0

[M] Change in coreboot[master]: soc/amd: Drop acpi_fill_madt_irqoverride()
by Kyösti Mälkki (Code Review) 27 Apr '23

27 Apr '23

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74357 ) Change subject: soc/amd: Drop acpi_fill_madt_irqoverride() ...................................................................... soc/amd: Drop acpi_fill_madt_irqoverride() It is unused. The use of field irq is problematic as it should appear relative to IOAPIC GSI bases in the devicetree. Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com&… [View More]gt; Reviewed-on: https://review.coreboot.org/c/coreboot/+/74357 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/common/block/include/amdblocks/chip.h M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c 8 files changed, 16 insertions(+), 43 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 732e736..3482bbb 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -25,8 +25,6 @@ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - current = acpi_fill_madt_irqoverride(current); - return current; } diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index 3ba9af6..aaa851e 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -16,27 +16,6 @@ return acpi_write_hpet(device, current, rsdp); } -unsigned long acpi_fill_madt_irqoverride(unsigned long current) -{ - const struct soc_amd_common_config *cfg = soc_get_common_config(); - unsigned int i; - uint8_t irq; - uint8_t flags; - - for (i = 0; i < ARRAY_SIZE(cfg->irq_override); ++i) { - irq = cfg->irq_override[i].irq; - flags = cfg->irq_override[i].flags; - - if (!flags) - continue; - - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, - irq, irq, flags); - } - - return current; -} - /* Used by \_SB.PCI0._CRS */ void acpi_fill_root_complex_tom(const struct device *device) { diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 9ffcb7e..9105184 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -54,7 +54,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -unsigned long acpi_fill_madt_irqoverride(unsigned long current); void acpi_fill_root_complex_tom(const struct device *device); uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index 46662fc..4135923 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -27,17 +27,6 @@ uint16_t fadt_boot_arch; uint32_t fadt_flags; - /** - * IRQ 0 - 15 have a default trigger of edge and default polarity of high. - * If you have a device that requires a different configuration you can override the - * settings here. - */ - struct { - uint8_t irq; - /* See MP_IRQ_* from acpi.h */ - uint8_t flags; - } irq_override[16]; - /* Audio Co-processor (ACP) configuration */ struct acp_config acp_config; }; diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index f5185d4..d961fcf 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -27,8 +27,6 @@ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - current = acpi_fill_madt_irqoverride(current); - return current; } diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index a8b04bf..fddc892 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -26,8 +26,6 @@ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - current = acpi_fill_madt_irqoverride(current); - return current; } diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index e011571..d067deb 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -27,8 +27,6 @@ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - current = acpi_fill_madt_irqoverride(current); - return current; } diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 9e74c6e..a5df99d 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -30,8 +30,6 @@ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, GNB_IO_APIC_ADDR); - current = acpi_fill_madt_irqoverride(current); - return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I460fd5fde3a7fba5518ccfc153a266d097a95a39 Gerrit-Change-Number: 74357 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

1 0

[XL] Change in coreboot[master]: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Lance Zhao, Philipp Hug, Tim Wawrzynczak, ron minnich. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74799 ) Change subject: ACPI,SMBIOS : Provide ACPI and SMBIOS supports for RISC-V ...................................................................... Patch Set 1: (97 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175071): https://review.coreboot.org/c/… [View More]

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023