coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[M] Change in coreboot[master]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Julius Werner. Hello Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74798 to look at the new patch set (#2). Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... arch/arm64: Add EL1/EL2/EL3 support for arm64 Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to read coreboot's current EL via the 'currentel' register and choose the appropriate ELx register. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e --- M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/ramdetect.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 8 files changed, 140 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74798/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 2 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by build bot (Jenkins) (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798 ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175068): https://review.coreboot.org/c/coreboot/+/74798/comment/6aa3b447_e88b7c29 PS1, Line 17: The strategy here, is to read coreboot's current EL via the 'appropiate' may be misspelled - perhaps 'appropriate'? -- To view, visit https://review.coreboot.org/c/coreboot/+/74798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 27 Apr 2023 00:48:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by David Milosevic (Code Review) 26 Apr '23

26 Apr '23

David Milosevic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74798 ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... arch/arm64: Add EL1/EL2/EL3 support for arm64 Currently, arch/arm64 requires coreboot to run on EL3 due to EL3 register access. This might be an issue when, for example, one boots into TF-A first and drops into EL2 for coreboot afterwards. This patch aims at making arch/arm64 more versatile by removing the current EL3 constraint and allowing arm64 coreboot to run on EL1, EL2 and EL3. The strategy here, is to read coreboot's current EL via the 'currentel' register and choose the appropiate ELx register. So, for example, when running coreboot on EL1, we would not access vbar_el3 or vbar_el2 but instead vbar_el1. This way, we don't generate faults when accessing higher-EL registers. Currently only tested on the qemu-aarch64 target. Exceptions were tested by enabling FATAL_ASSERTS. Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e --- M src/arch/arm64/armv8/cache.c M src/arch/arm64/armv8/exception.c M src/arch/arm64/armv8/mmu.c M src/arch/arm64/include/armv8/arch/cache.h M src/arch/arm64/include/armv8/arch/lib_helpers.h M src/arch/arm64/ramdetect.c M src/arch/arm64/transition.c M src/arch/arm64/transition_asm.S 8 files changed, 140 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/74798/1 diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index ae0729e..85ce683 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -90,10 +90,13 @@ */ void arch_segment_loaded(uintptr_t start, size_t size, int flags) { - uint32_t sctlr = raw_read_sctlr_el3(); + uint32_t sctlr = raw_read_sctlr_current_el(); + if (sctlr & SCTLR_C) dcache_clean_by_mva((void *)start, size); else if (sctlr & SCTLR_I) dcache_clean_invalidate_by_mva((void *)start, size); + icache_invalidate_all(); + } diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 80b619d..a3113d6 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -51,9 +51,10 @@ struct regs *regs = &exc_state->regs; printk(BIOS_DEBUG, "ELR = 0x%016llx ESR = 0x%08llx\n", - elx->elr, raw_read_esr_el3()); + elx->elr, raw_read_esr_current_el()); printk(BIOS_DEBUG, "FAR = 0x%016llx SPSR = 0x%08llx\n", - raw_read_far_el3(), raw_read_spsr_el3()); + raw_read_far_current_el(), raw_read_spsr_current_el()); + for (i = 0; i < 30; i += 2) { printk(BIOS_DEBUG, "X%02d = 0x%016llx X%02d = 0x%016llx\n", @@ -162,7 +163,8 @@ { /* Update instruction pointer to next instrution. */ state->elx.elr += sizeof(uint32_t); - raw_write_elr_el3(state->elx.elr); + raw_write_elr_current_el(state->elx.elr); + return EXC_RET_HANDLED; } diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 61ca49f..8b38c13 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -224,7 +224,12 @@ /* ARMv8 MMUs snoop L1 data cache, no need to flush it. */ dsb(); - tlbiall_el3(); + + if (current_el() == EL2) + tlbiall_el2(); + else + tlbiall_el3(); + dsb(); isb(); } @@ -245,15 +250,15 @@ assert((u8 *)root == _ttb); /* Initialize TTBR */ - raw_write_ttbr0_el3((uintptr_t)root); + raw_write_ttbr0_current_el((uintptr_t)root); /* Initialize MAIR indices */ - raw_write_mair_el3(MAIR_ATTRIBUTES); + raw_write_mair_current_el(MAIR_ATTRIBUTES); /* Initialize TCR flags */ - raw_write_tcr_el3(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | - TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB | - TCR_TBI_USED); + raw_write_tcr_current_el(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | + TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB | + TCR_TBI_USED); } /* Func : mmu_save_context @@ -264,10 +269,10 @@ assert(mmu_context); /* Back-up MAIR_ATTRIBUTES */ - mmu_context->mair = raw_read_mair_el3(); + mmu_context->mair = raw_read_mair_current_el(); /* Back-up TCR value */ - mmu_context->tcr = raw_read_tcr_el3(); + mmu_context->tcr = raw_read_tcr_current_el(); } /* Func : mmu_restore_context @@ -278,13 +283,13 @@ assert(mmu_context); /* Restore TTBR */ - raw_write_ttbr0_el3((uintptr_t)_ttb); + raw_write_ttbr0_current_el((uintptr_t)_ttb); /* Restore MAIR indices */ - raw_write_mair_el3(mmu_context->mair); + raw_write_mair_current_el(mmu_context->mair); /* Restore TCR flags */ - raw_write_tcr_el3(mmu_context->tcr); + raw_write_tcr_current_el(mmu_context->tcr); /* invalidate tlb since ttbr is updated. */ tlb_invalidate_all(); @@ -295,8 +300,8 @@ assert_correct_ttb_mapping(_ttb); assert_correct_ttb_mapping(_ettb - 1); - uint32_t sctlr = raw_read_sctlr_el3(); - sctlr |= SCTLR_C | SCTLR_M | SCTLR_I; - raw_write_sctlr_el3(sctlr); + uint32_t sctlr = raw_read_sctlr_current_el(); + raw_write_sctlr_current_el(sctlr | SCTLR_C | SCTLR_M | SCTLR_I); + isb(); } diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index bb9d6fe..a972007 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -34,7 +34,12 @@ static inline void tlb_invalidate_all(void) { /* TLBIALL includes dTLB and iTLB on systems that have them. */ - tlbiall_el3(); + + if (current_el() == EL2) + tlbiall_el2(); + else + tlbiall_el3(); + dsb(); isb(); } diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 4b3730f..d62c824 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -113,10 +113,53 @@ : : "r" (value) : "memory"); \ } +/* Forward Declaration for MAKE_REGISTER_ACCESSORS_CURRENT_EL */ +static inline u64 current_el(void); +/* + * In order to allow easy access to current EL's registers, + * we export following two functions for each EL register, that + * was passed to the MAKE_REGISTER_ACCESSORS_CURRENT_EL macro. Doing + * this, eliminates, or at least hides, repetitive branching on the + * current EL across the arm64 codebase. + * + * MAKE_REGISTER_ACCESSORS_CURRENT_EL was hooked into MAKE_REGISTER_ACCESSORS_EL123, + * in order to automatically generate current_el accessors only for registers which + * exist on EL1, EL2 and EL3. + * + * Note, that we don't handle EL0 here, as EL0 has no access + * to the currentel register. + * + * Important: + * - target register should be specified without the '_elx' suffix + * - only registers which exist in EL1, EL2 and EL3 should be passed + * to the MAKE_REGISTER_ACCESSORS_CURRENT_EL macro + */ +#define MAKE_REGISTER_ACCESSORS_CURRENT_EL(reg) \ + static inline uint64_t raw_read_##reg##_current_el(void) \ + { \ + uint64_t exception_level = current_el(); \ + if (exception_level == EL1) \ + return raw_read_##reg##_el1(); \ + else if (exception_level == EL2) \ + return raw_read_##reg##_el2(); \ + return raw_read_##reg##_el3(); \ + } \ + static inline void raw_write_##reg##_current_el(uint64_t value) \ + { \ + uint64_t exception_level = current_el(); \ + if (exception_level == EL1) \ + raw_write_##reg##_el1(value); \ + else if (exception_level == EL2) \ + raw_write_##reg##_el2(value); \ + else \ + raw_write_##reg##_el3(value); \ + } + #define MAKE_REGISTER_ACCESSORS_EL123(reg) \ MAKE_REGISTER_ACCESSORS(reg##_el1) \ MAKE_REGISTER_ACCESSORS(reg##_el2) \ - MAKE_REGISTER_ACCESSORS(reg##_el3) + MAKE_REGISTER_ACCESSORS(reg##_el3) \ + MAKE_REGISTER_ACCESSORS_CURRENT_EL(reg) /* Architectural register accessors */ MAKE_REGISTER_ACCESSORS_EL123(actlr) @@ -196,6 +239,15 @@ MAKE_REGISTER_ACCESSORS(vtcr_el2) MAKE_REGISTER_ACCESSORS(vttbr_el2) +/* Exception Level functions */ +static inline u64 current_el(void) +{ + register uint64_t x0 __asm__("x0"); + __asm__ __volatile__("mrs x0, CurrentEL;" + : : : "%x0"); + return x0 >> 2; +} + /* Special DAIF accessor functions */ static inline void enable_debug_exceptions(void) { diff --git a/src/arch/arm64/ramdetect.c b/src/arch/arm64/ramdetect.c index 2f6a1cd..cfcc055 100644 --- a/src/arch/arm64/ramdetect.c +++ b/src/arch/arm64/ramdetect.c @@ -13,12 +13,13 @@ static int abort_checker(struct exc_state *state, uint64_t vector_id) { - if (raw_read_esr_el3() >> 26 != 0x25) + if (raw_read_esr_current_el() >> 26 != 0x25) return EXC_RET_IGNORED; /* Not a data abort. */ abort_state = ABORT_CHECKER_TRIGGERED; state->elx.elr += sizeof(uint32_t); /* Jump over faulting instruction. */ - raw_write_elr_el3(state->elx.elr); + raw_write_elr_current_el(state->elx.elr); + return EXC_RET_HANDLED; } diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index e5c83bf..72582d4 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -17,7 +17,9 @@ struct regs *regs = &exc_state->regs; uint8_t elx_mode; - elx->spsr = raw_read_spsr_el3(); + elx->spsr = raw_read_spsr_current_el(); + elx->elr = raw_read_elr_current_el(); + elx_mode = get_mode_from_spsr(elx->spsr); if (elx_mode == SPSR_USE_H) @@ -25,8 +27,6 @@ else regs->sp = raw_read_sp_el0(); - elx->elr = raw_read_elr_el3(); - exc_dispatch(exc_state, id); } diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S index 73a6fb6..818d103 100644 --- a/src/arch/arm64/transition_asm.S +++ b/src/arch/arm64/transition_asm.S @@ -142,7 +142,7 @@ ENDPROC(exc_exit) /* - * exception_init_asm: Initialize VBAR and point SP_EL3 to exception stack. + * exception_init_asm: Initialize VBAR and point SP_ELx to exception stack. * Also unmask aborts now that we can report them. x0 = end of exception stack */ ENTRY(exception_init_asm) @@ -151,8 +151,27 @@ msr SPSel, #SPSR_USE_L adr x0, exc_vectors + + mrs x1, currentel + ubfx w1, w1, #2, #8 + cmp w1, #0x1 + b.ne el2_or_el3 +el1: + msr vbar_el1, x0 + b end + +el2_or_el3: + cmp w1, #0x2 + b.ne el3 + +el2: + msr vbar_el2, x0 + b end + +el3: msr vbar_el3, x0 +end: msr DAIFClr, #0xf dsb sy -- To view, visit https://review.coreboot.org/c/coreboot/+/74798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
by Julius Werner (Code Review) 26 Apr '23

26 Apr '23

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74742 ) Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern ...................................................................... util/cbmem: Add REG_NEWLINE flag to fix matching pattern Match-any-character operators (eg. ".*") shall not match newline characters for BANNER_REGEX, since given regular expression matches newline explicitly. Add REG_NEWLINE flag to `regcomp` call. BUG=b:278718871 TEST=Boot firmware on skyrim, reboot. Run `cbmem -2`. `cbmem -2` returns second-to-last boot log. Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Signed-off-by: Konrad Adamczyk <konrada(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74742 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M util/cbmem/cbmem.c 1 file changed, 26 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index c0b39ea..060f88c 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1001,7 +1001,7 @@ for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; - int res = regcomp(&re, regex[i], REG_EXTENDED); + int res = regcomp(&re, regex[i], REG_EXTENDED | REG_NEWLINE); assert(res == 0); /* Keep looking for matches so we find the last one. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Gerrit-Change-Number: 74742 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: util/cbmem: Add REG_NEWLINE flag to fix matching pattern
by Julius Werner (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Konrad Adamczyk, Raul Rangel, Jakub Czapiga, Grzegorz Bernacki. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74742 ) Change subject: util/cbmem: Add REG_NEWLINE flag to fix matching pattern ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74742/comment/8c92478a_70056e57 PS1, Line 13: REG_NEWLINE > Thanks for the history and the great explanation. Wow, great find, thanks! So just to clarify my understanding, the switch to REG_EXTENDED actually has nothing to do with the problem, it doesn't affect the newline behavior. And the fact that it accidentally matches all the way to `"Starting depthcharge...\n"` is also irrelevant to the user-visible bug (even though it is unintended, and a bit wasteful). The only real issue is that the `.?` introduced may match a newline, and this will result in `cbmem -2` not displaying the correct boot iff the log does not contain loglevel markers. Part of the problem was also that CB:33779 introduced the `.*` when the original patch had used `[^\n]*` for the same purpose. I guess REG_NEWLINE is a better way to fix the same problem, though. Maybe we should change the `[^\n]*` to `.*` for consistency now, because it doesn't make a difference anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/74742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e924349ead0fa7eea8b9ad5161138a4c4946ade Gerrit-Change-Number: 74742 Gerrit-PatchSet: 1 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Comment-Date: Thu, 27 Apr 2023 00:38:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Konrad Adamczyk <konrada(a)google.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/taeko: Disable C1E for RPL CPU
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, YH Lin, Joey Peng, Subrata Banik, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74786 ) Change subject: mb/google/brya/var/taeko: Disable C1E for RPL CPU ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e4c74aa288f1c824c5e7ce83090cf61d7653183 Gerrit-Change-Number: 74786 Gerrit-PatchSet: 2 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 00:28:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Add option to disable C1E
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: YH Lin, Tarun Tuli, Joey Peng, Paul Menzel, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Add option to disable C1E ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/74727/comment/cf7393ce_801e67b6 PS7, Line 690: c1e Change the name to c1e_enable? And use bool for it? -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 7 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 00:27:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIG
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, YH Lin. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74775 ) Change subject: mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIG ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5 Gerrit-Change-Number: 74775 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Thu, 27 Apr 2023 00:18:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Martin Roth, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74791 ) Change subject: arch/x86/include/pci_io_cfg: introduce PCI_IO_CONFIG_[INDEX,DATA] define ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6f6f058180cf36cae7921ce3c7aaf1a0c75c7b9 Gerrit-Change-Number: 74791 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 27 Apr 2023 00:11:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Select FSP MULTIPHASE SI INIT RETURN BROKEN config
by Eric Lai (Code Review) 26 Apr '23

26 Apr '23

Attention is currently required from: Subrata Banik, Derek Huang, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74785 ) Change subject: soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: nice work! Can we have decode for the reset type from FSP instead 40000003 something like this. -- To view, visit https://review.coreboot.org/c/coreboot/+/74785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963 Gerrit-Change-Number: 74785 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 00:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023