coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

1 participants
5761 discussions

[S] Change in coreboot[master]: src/mainboard/rex: Perform CSE FW update in RAMSTAGE
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74764 ) Change subject: src/mainboard/rex: Perform CSE FW update in RAMSTAGE ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/Kconfig: https://review.coreboot.org/c/coreboot/+/74764/comment/03352c4f_9225eb60 PS3, Line 42: select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE please follow the order -- To view, visit https://review.coreboot.org/c/coreboot/+/74764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36e59b0c61e852d5c3b7357292039211fcdbb0aa Gerrit-Change-Number: 74764 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 10:13:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex/variants/screebo: Generate RAM IDs
by Kapil Porwal (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Kun Liu. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, Kun Liu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74802 to look at the new patch set (#2). Change subject: mb/google/rex/variants/screebo: Generate RAM IDs ...................................................................... mb/google/rex/variants/screebo: Generate RAM IDs Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 --- M src/mainboard/google/rex/variants/screebo/memory/Makefile.inc M src/mainboard/google/rex/variants/screebo/memory/dram_id.generated.txt M src/mainboard/google/rex/variants/screebo/memory/mem_parts_used.txt 3 files changed, 39 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/74802/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Gerrit-Change-Number: 74802 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Add config option to choose CSE FW sync in ROMS...
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Anil Kumar K, Tarun Tuli, Jamie Ryu, Paul Menzel, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74763 ) Change subject: soc/intel/meteorlake: Add config option to choose CSE FW sync in ROMSTAGE ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74763/comment/b8e366d2_7c98a58d PS5, Line 7: Add config option to choose CSE FW sync in : ROMSTAGE Use config to perform CSE sync at romstage -- To view, visit https://review.coreboot.org/c/coreboot/+/74763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e603a2ecf1a67ee7c683b440072889d137f9de0 Gerrit-Change-Number: 74763 Gerrit-PatchSet: 5 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 10:10:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/cmn/cse: Remove dependency on ME_RW compression for CSE FW ...
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Bora Guvendik, Anil Kumar K, Hannah Williams, Jérémy Compostella, Paul Menzel, Kapil Porwal, Rizwan Qureshi, Sridhar Siricilla, Krishna P Bhat D. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74796 ) Change subject: soc/intel/cmn/cse: Remove dependency on ME_RW compression for CSE FW sync ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74796/comment/d6e176e4_3e706e28 PS6, Line 7: Remove dependency on ME_RW compression for CSE FW : sync soc/intel/cmn/cse: Decouple `ME_RW compression` from `CSE RW Sync` -- To view, visit https://review.coreboot.org/c/coreboot/+/74796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Gerrit-Change-Number: 74796 Gerrit-PatchSet: 6 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 10:08:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: mb/google/dedede/var/boxy: Update devicetree and GPIO table
by Kevin3 Yang (Code Review) 27 Apr '23

27 Apr '23

Kevin3 Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74626 ) Change subject: mb/google/dedede/var/boxy: Update devicetree and GPIO table ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/74626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Gerrit-Change-Number: 74626 Gerrit-PatchSet: 9 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 09:34:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3084_85 to 3143_80
by build bot (Jenkins) (Code Review) 27 Apr '23

27 Apr '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74803 ) Change subject: vc/intel/fsp/mtl: Update header files from 3084_85 to 3143_80 ...................................................................... Patch Set 1: (3 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175093): https://review.coreboot.org/c/coreboot/+/74803/comment/4f29fd83_99eedfcc PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175093): https://review.coreboot.org/c/coreboot/+/74803/comment/5fc486ca_6f9ebab5 PS1, Line 12: 1. Name change of UPD from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175093): https://review.coreboot.org/c/coreboot/+/74803/comment/355aa19e_a8cd06f4 PS1, Line 13: 2. Name change of UPD from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Gerrit-Change-Number: 74803 Gerrit-PatchSet: 1 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Apr 2023 09:33:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 3084_85 to 3143_80
by Kilari Raasi (Code Review) 27 Apr '23

27 Apr '23

Kilari Raasi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74803 ) Change subject: vc/intel/fsp/mtl: Update header files from 3084_85 to 3143_80 ...................................................................... vc/intel/fsp/mtl: Update header files from 3084_85 to 3143_80 Update header files for FSP for Meteor Lake platform to version 3143_80, previous version being 3084_85. FSPM: 1. Name change of UPD from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' 2. Name change of UPD from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' 3. Name change of UPD from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage' 4. Address offset changes FSPS: 1. Remove deprecated UPD 'PcieDpc' 2. Address offset changes BUG=b:279511709 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 2 files changed, 795 insertions(+), 777 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/74803/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index f6076c9..c4471d6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -792,7 +792,7 @@ /** Offset 0x02A0 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum **/ - UINT16 GtExtraTurboVoltage; + UINT16 GtAdaptiveVoltage; /** Offset 0x02A2 - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum @@ -1233,11 +1233,11 @@ **/ UINT16 CoreVoltageOverride; -/** Offset 0x0408 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. +/** Offset 0x0408 - Core Turbo Adaptive Voltage + Adaptive voltage applied to the cpu core when the cpu is operating in turbo mode. Valid Range 0 to 2000 **/ - UINT16 CoreVoltageAdaptive; + UINT16 CoreAdaptiveVoltage; /** Offset 0x040A - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 @@ -1274,11 +1274,11 @@ **/ UINT16 RingVoltageOverride; -/** Offset 0x0412 - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. +/** Offset 0x0412 - Ring Turbo Adaptive Voltage + Adaptive voltage applied to the cpu ring when the cpu is operating in turbo mode. Valid Range 0 to 2000 **/ - UINT16 RingVoltageAdaptive; + UINT16 RingAdaptiveVoltage; /** Offset 0x0414 - Ring Turbo voltage Offset The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 @@ -1430,19 +1430,19 @@ /** Offset 0x06B0 - Reserved **/ - UINT8 Reserved34[232]; + UINT8 Reserved34[240]; -/** Offset 0x0798 - BiosGuard +/** Offset 0x07A0 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x0799 +/** Offset 0x07A1 **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x079A - Txt +/** Offset 0x07A2 - Txt Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable @@ -1450,1252 +1450,1252 @@ **/ UINT8 Txt; -/** Offset 0x079B - Reserved +/** Offset 0x07A3 - Reserved **/ UINT8 Reserved35; -/** Offset 0x079C - PrmrrSize +/** Offset 0x07A4 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable **/ UINT32 PrmrrSize; -/** Offset 0x07A0 - SinitMemorySize +/** Offset 0x07A8 - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x07A4 - Reserved +/** Offset 0x07AC - Reserved **/ UINT8 Reserved36[4]; -/** Offset 0x07A8 - TxtDprMemoryBase +/** Offset 0x07B0 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable **/ UINT64 TxtDprMemoryBase; -/** Offset 0x07B0 - TxtHeapMemorySize +/** Offset 0x07B8 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x07B4 - TxtDprMemorySize +/** Offset 0x07BC - TxtDprMemorySize Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x07B8 - BiosAcmBase +/** Offset 0x07C0 - BiosAcmBase Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable **/ UINT32 BiosAcmBase; -/** Offset 0x07BC - BiosAcmSize +/** Offset 0x07C4 - BiosAcmSize Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable **/ UINT32 BiosAcmSize; -/** Offset 0x07C0 - ApStartupBase +/** Offset 0x07C8 - ApStartupBase Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable **/ UINT32 ApStartupBase; -/** Offset 0x07C4 - TgaSize +/** Offset 0x07CC - TgaSize Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable **/ UINT32 TgaSize; -/** Offset 0x07C8 - TxtLcpPdBase +/** Offset 0x07D0 - TxtLcpPdBase Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable **/ UINT64 TxtLcpPdBase; -/** Offset 0x07D0 - TxtLcpPdSize +/** Offset 0x07D8 - TxtLcpPdSize Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable **/ UINT64 TxtLcpPdSize; -/** Offset 0x07D8 - IsTPMPresence +/** Offset 0x07E0 - IsTPMPresence IsTPMPresence default values **/ UINT8 IsTPMPresence; -/** Offset 0x07D9 - Reserved +/** Offset 0x07E1 - Reserved **/ UINT8 Reserved37[32]; -/** Offset 0x07F9 - Enable PCH HSIO PCIE Rx Set Ctle +/** Offset 0x0801 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtleEnable[28]; -/** Offset 0x0815 - PCH HSIO PCIE Rx Set Ctle Value +/** Offset 0x081D - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value. **/ UINT8 PchPcieHsioRxSetCtle[28]; -/** Offset 0x0831 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override +/** Offset 0x0839 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; -/** Offset 0x084D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x0855 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; -/** Offset 0x0869 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override +/** Offset 0x0871 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; -/** Offset 0x0885 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value +/** Offset 0x088D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; -/** Offset 0x08A1 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override +/** Offset 0x08A9 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; -/** Offset 0x08BD - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value +/** Offset 0x08C5 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; -/** Offset 0x08D9 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x08E1 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; -/** Offset 0x08F5 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value +/** Offset 0x08FD - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen1DeEmph[28]; -/** Offset 0x0911 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override +/** Offset 0x0919 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; -/** Offset 0x092D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value +/** Offset 0x0935 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; -/** Offset 0x0949 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override +/** Offset 0x0951 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; -/** Offset 0x0965 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value +/** Offset 0x096D - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. **/ UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; -/** Offset 0x0981 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override +/** Offset 0x0989 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; -/** Offset 0x0989 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value +/** Offset 0x0991 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. **/ UINT8 PchSataHsioRxGen1EqBoostMag[8]; -/** Offset 0x0991 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override +/** Offset 0x0999 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; -/** Offset 0x0999 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value +/** Offset 0x09A1 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. **/ UINT8 PchSataHsioRxGen2EqBoostMag[8]; -/** Offset 0x09A1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override +/** Offset 0x09A9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; -/** Offset 0x09A9 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value +/** Offset 0x09B1 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. **/ UINT8 PchSataHsioRxGen3EqBoostMag[8]; -/** Offset 0x09B1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override +/** Offset 0x09B9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; -/** Offset 0x09B9 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value +/** Offset 0x09C1 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchSataHsioTxGen1DownscaleAmp[8]; -/** Offset 0x09C1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override +/** Offset 0x09C9 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; -/** Offset 0x09C9 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value +/** Offset 0x09D1 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchSataHsioTxGen2DownscaleAmp[8]; -/** Offset 0x09D1 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override +/** Offset 0x09D9 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; -/** Offset 0x09D9 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value +/** Offset 0x09E1 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. **/ UINT8 PchSataHsioTxGen3DownscaleAmp[8]; -/** Offset 0x09E1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x09E9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen1DeEmphEnable[8]; -/** Offset 0x09E9 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting +/** Offset 0x09F1 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchSataHsioTxGen1DeEmph[8]; -/** Offset 0x09F1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x09F9 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen2DeEmphEnable[8]; -/** Offset 0x09F9 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting +/** Offset 0x0A01 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchSataHsioTxGen2DeEmph[8]; -/** Offset 0x0A01 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override +/** Offset 0x0A09 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0: Disable; 1: Enable. **/ UINT8 PchSataHsioTxGen3DeEmphEnable[8]; -/** Offset 0x0A09 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting +/** Offset 0x0A11 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. **/ UINT8 PchSataHsioTxGen3DeEmph[8]; -/** Offset 0x0A11 - PCH LPC Enhance the port 8xh decoding +/** Offset 0x0A19 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h. $EN_DIS **/ UINT8 PchLpcEnhancePort8xhDecoding; -/** Offset 0x0A12 - PCH Port80 Route +/** Offset 0x0A1A - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. $EN_DIS **/ UINT8 PchPort80Route; -/** Offset 0x0A13 - Enable SMBus ARP support +/** Offset 0x0A1B - Enable SMBus ARP support Enable SMBus ARP support. $EN_DIS **/ UINT8 SmbusArpEnable; -/** Offset 0x0A14 - Number of RsvdSmbusAddressTable. +/** Offset 0x0A1C - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0A15 - Reserved +/** Offset 0x0A1D - Reserved **/ UINT8 Reserved38; -/** Offset 0x0A16 - SMBUS Base Address +/** Offset 0x0A1E - SMBUS Base Address SMBUS Base Address (IO space). **/ UINT16 PchSmbusIoBase; -/** Offset 0x0A18 - Enable SMBus Alert Pin +/** Offset 0x0A20 - Enable SMBus Alert Pin Enable SMBus Alert Pin. $EN_DIS **/ UINT8 PchSmbAlertEnable; -/** Offset 0x0A19 - Usage type for ClkSrc - 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used +/** Offset 0x0A21 - Usage type for SOC/IOE ClkSrc + 0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ - UINT8 PcieClkSrcUsage[18]; + UINT8 PcieClkSrcUsage[16]; -/** Offset 0x0A2B - Reserved +/** Offset 0x0A31 - Reserved **/ - UINT8 Reserved39[14]; + UINT8 Reserved39[16]; -/** Offset 0x0A39 - ClkReq-to-ClkSrc mapping +/** Offset 0x0A41 - SOC/IOE ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ - UINT8 PcieClkSrcClkReq[18]; + UINT8 PcieClkSrcClkReq[16]; -/** Offset 0x0A4B - Reserved +/** Offset 0x0A51 - Reserved **/ - UINT8 Reserved40[57]; + UINT8 Reserved40[59]; -/** Offset 0x0A84 - Enable SOC/IOE PCIE RP Mask +/** Offset 0x0A8C - Enable SOC/IOE PCIE RP Mask Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT16 PcieRpEnableMask; -/** Offset 0x0A86 - VC Type +/** Offset 0x0A8E - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. 0: VC0, 1: VC1 **/ UINT8 PchHdaVcType; -/** Offset 0x0A87 - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x0A8F - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x0A88 - Enable HD Audio Link +/** Offset 0x0A90 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x0A89 - Enable HDA SDI lanes +/** Offset 0x0A91 - Enable HDA SDI lanes Enable/disable HDA SDI lanes. **/ UINT8 PchHdaSdiEnable[2]; -/** Offset 0x0A8B - HDA Power/Clock Gating (PGD/CGD) +/** Offset 0x0A93 - HDA Power/Clock Gating (PGD/CGD) Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE. 0: POR, 1: Force Enable, 2: Force Disable **/ UINT8 PchHdaTestPowerClockGating; -/** Offset 0x0A8C - Enable HD Audio DMIC_N Link +/** Offset 0x0A94 - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x0A8E - Reserved +/** Offset 0x0A96 - Reserved **/ UINT8 Reserved41[2]; -/** Offset 0x0A90 - DMIC<N> ClkA Pin Muxing (N - DMIC number) +/** Offset 0x0A98 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x0A98 - DMIC<N> ClkB Pin Muxing +/** Offset 0x0AA0 - DMIC<N> ClkB Pin Muxing Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* **/ UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; -/** Offset 0x0AA0 - Enable HD Audio DSP +/** Offset 0x0AA8 - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x0AA1 - Reserved +/** Offset 0x0AA9 - Reserved **/ UINT8 Reserved42[3]; -/** Offset 0x0AA4 - DMIC<N> Data Pin Muxing +/** Offset 0x0AAC - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x0AAC - Enable HD Audio SSP0 Link +/** Offset 0x0AB4 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x0AB2 - Enable HD Audio SoundWire#N Link +/** Offset 0x0ABA - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x0AB6 - iDisp-Link Frequency +/** Offset 0x0ABE - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x0AB7 - Reserved +/** Offset 0x0ABF - Reserved **/ UINT8 Reserved43; -/** Offset 0x0AB8 - iDisp-Link T-mode +/** Offset 0x0AC0 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x0AB9 - iDisplay Audio Codec disconnection +/** Offset 0x0AC1 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x0ABA - Reserved +/** Offset 0x0AC2 - Reserved **/ UINT8 Reserved44[6]; -/** Offset 0x0AC0 - CNVi DDR RFI Mitigation +/** Offset 0x0AC8 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviDdrRfim; -/** Offset 0x0AC1 - Reserved +/** Offset 0x0AC9 - Reserved **/ UINT8 Reserved45[11]; -/** Offset 0x0ACC - Debug Interfaces +/** Offset 0x0AD4 - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x0ACD - Serial Io Uart Debug Controller Number +/** Offset 0x0AD5 - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x0ACE - Serial Io Uart Debug Auto Flow +/** Offset 0x0AD6 - Serial Io Uart Debug Auto Flow Enables UART hardware flow control, CTS and RTS lines. $EN_DIS **/ UINT8 SerialIoUartDebugAutoFlow; -/** Offset 0x0ACF - Reserved +/** Offset 0x0AD7 - Reserved **/ UINT8 Reserved46; -/** Offset 0x0AD0 - Serial Io Uart Debug BaudRate +/** Offset 0x0AD8 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 **/ UINT32 SerialIoUartDebugBaudRate; -/** Offset 0x0AD4 - Serial Io Uart Debug Parity +/** Offset 0x0ADC - Serial Io Uart Debug Parity Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity **/ UINT8 SerialIoUartDebugParity; -/** Offset 0x0AD5 - Serial Io Uart Debug Stop Bits +/** Offset 0x0ADD - Serial Io Uart Debug Stop Bits Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits **/ UINT8 SerialIoUartDebugStopBits; -/** Offset 0x0AD6 - Serial Io Uart Debug Data Bits +/** Offset 0x0ADE - Serial Io Uart Debug Data Bits Set default word length. 0: Default, 5,6,7,8 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x0AD7 - Reserved +/** Offset 0x0ADF - Reserved **/ UINT8 Reserved47; -/** Offset 0x0AD8 - Serial Io Uart Debug Mmio Base +/** Offset 0x0AE0 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode = SerialIoUartPci. **/ UINT32 SerialIoUartDebugMmioBase; -/** Offset 0x0ADC - ISA Serial Base selection +/** Offset 0x0AE4 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x0ADD - Reserved +/** Offset 0x0AE5 - Reserved **/ UINT8 Reserved48; -/** Offset 0x0ADE - Ring PLL voltage offset +/** Offset 0x0AE6 - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 RingPllVoltageOffset; -/** Offset 0x0ADF - System Agent PLL voltage offset +/** Offset 0x0AE7 - System Agent PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 SaPllVoltageOffset; -/** Offset 0x0AE0 - Reserved +/** Offset 0x0AE8 - Reserved **/ UINT8 Reserved49; -/** Offset 0x0AE1 - Memory Controller PLL voltage offset +/** Offset 0x0AE9 - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 **/ UINT8 McPllVoltageOffset; -/** Offset 0x0AE2 - TCSS Thunderbolt PCIE Root Port 0 Enable +/** Offset 0x0AEA - TCSS Thunderbolt PCIE Root Port 0 Enable Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie0En; -/** Offset 0x0AE3 - TCSS Thunderbolt PCIE Root Port 1 Enable +/** Offset 0x0AEB - TCSS Thunderbolt PCIE Root Port 1 Enable Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie1En; -/** Offset 0x0AE4 - TCSS Thunderbolt PCIE Root Port 2 Enable +/** Offset 0x0AEC - TCSS Thunderbolt PCIE Root Port 2 Enable Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie2En; -/** Offset 0x0AE5 - TCSS Thunderbolt PCIE Root Port 3 Enable +/** Offset 0x0AED - TCSS Thunderbolt PCIE Root Port 3 Enable Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie3En; -/** Offset 0x0AE6 - TCSS USB HOST (xHCI) Enable +/** Offset 0x0AEE - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x0AE7 - TCSS USB DEVICE (xDCI) Enable +/** Offset 0x0AEF - TCSS USB DEVICE (xDCI) Enable Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled $EN_DIS **/ UINT8 TcssXdciEn; -/** Offset 0x0AE8 - TCSS DMA0 Enable +/** Offset 0x0AF0 - TCSS DMA0 Enable Set TCSS DMA0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma0En; -/** Offset 0x0AE9 - TCSS DMA1 Enable +/** Offset 0x0AF1 - TCSS DMA1 Enable Set TCSS DMA1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma1En; -/** Offset 0x0AEA - PcdSerialDebugBaudRate +/** Offset 0x0AF2 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200 **/ UINT8 PcdSerialDebugBaudRate; -/** Offset 0x0AEB - HobBufferSize +/** Offset 0x0AF3 - HobBufferSize Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value **/ UINT8 HobBufferSize; -/** Offset 0x0AEC - Early Command Training +/** Offset 0x0AF4 - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x0AED - SenseAmp Offset Training +/** Offset 0x0AF5 - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS **/ UINT8 SOT; -/** Offset 0x0AEE - Early ReadMPR Timing Centering 2D +/** Offset 0x0AF6 - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS **/ UINT8 ERDMPRTC2D; -/** Offset 0x0AEF - Read MPR Training +/** Offset 0x0AF7 - Read MPR Training Enables/Disable Read MPR Training $EN_DIS **/ UINT8 RDMPRT; -/** Offset 0x0AF0 - Receive Enable Training +/** Offset 0x0AF8 - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS **/ UINT8 RCVET; -/** Offset 0x0AF1 - Jedec Write Leveling +/** Offset 0x0AF9 - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS **/ UINT8 JWRL; -/** Offset 0x0AF2 - Early Write Time Centering 2D +/** Offset 0x0AFA - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS **/ UINT8 EWRTC2D; -/** Offset 0x0AF3 - Early Read Time Centering 2D +/** Offset 0x0AFB - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS **/ UINT8 ERDTC2D; -/** Offset 0x0AF4 - Reserved +/** Offset 0x0AFC - Reserved **/ UINT8 Reserved50; -/** Offset 0x0AF5 - Write Timing Centering 1D +/** Offset 0x0AFD - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS **/ UINT8 WRTC1D; -/** Offset 0x0AF6 - Write Voltage Centering 1D +/** Offset 0x0AFE - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS **/ UINT8 WRVC1D; -/** Offset 0x0AF7 - Read Timing Centering 1D +/** Offset 0x0AFF - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS **/ UINT8 RDTC1D; -/** Offset 0x0AF8 - Read Voltage Centering 1D +/** Offset 0x0B00 - Read Voltage Centering 1D Enable/Disable Read Voltage Centering 1D $EN_DIS **/ UINT8 RDVC1D; -/** Offset 0x0AF9 - Reserved +/** Offset 0x0B01 - Reserved **/ UINT8 Reserved51[10]; -/** Offset 0x0B03 - Read Equalization Training +/** Offset 0x0B0B - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS **/ UINT8 RDEQT; -/** Offset 0x0B04 - Reserved +/** Offset 0x0B0C - Reserved **/ UINT8 Reserved52[2]; -/** Offset 0x0B06 - Write Timing Centering 2D +/** Offset 0x0B0E - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS **/ UINT8 WRTC2D; -/** Offset 0x0B07 - Read Timing Centering 2D +/** Offset 0x0B0F - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS **/ UINT8 RDTC2D; -/** Offset 0x0B08 - Write Voltage Centering 2D +/** Offset 0x0B10 - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS **/ UINT8 WRVC2D; -/** Offset 0x0B09 - Read Voltage Centering 2D +/** Offset 0x0B11 - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS **/ UINT8 RDVC2D; -/** Offset 0x0B0A - Reserved +/** Offset 0x0B12 - Reserved **/ UINT8 Reserved53; -/** Offset 0x0B0B - Command Voltage Centering +/** Offset 0x0B13 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS **/ UINT8 CMDVC; -/** Offset 0x0B0C - Late Command Training +/** Offset 0x0B14 - Late Command Training Enables/Disable Late Command Training $EN_DIS **/ UINT8 LCT; -/** Offset 0x0B0D - Turn Around Timing Training +/** Offset 0x0B15 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS **/ UINT8 TAT; -/** Offset 0x0B0E - Rank Margin Tool +/** Offset 0x0B16 - Rank Margin Tool Enable/disable Rank Margin Tool $EN_DIS **/ UINT8 RMT; -/** Offset 0x0B0F - Reserved +/** Offset 0x0B17 - Reserved **/ UINT8 Reserved54; -/** Offset 0x0B10 - DIMM SPD Alias Test +/** Offset 0x0B18 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS **/ UINT8 ALIASCHK; -/** Offset 0x0B11 - Retrain Margin Check +/** Offset 0x0B19 - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS **/ UINT8 RMC; -/** Offset 0x0B12 - Reserved +/** Offset 0x0B1A - Reserved **/ UINT8 Reserved55; -/** Offset 0x0B13 - Dimm ODT Training +/** Offset 0x0B1B - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS **/ UINT8 DIMMODTT; -/** Offset 0x0B14 - DIMM RON Training +/** Offset 0x0B1C - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS **/ UINT8 DIMMRONT; -/** Offset 0x0B15 - TxDqTCO Comp Training +/** Offset 0x0B1D - TxDqTCO Comp Training Enable/Disable TxDqTCO Comp Training $EN_DIS **/ UINT8 TXTCO; -/** Offset 0x0B16 - ClkTCO Comp Training +/** Offset 0x0B1E - ClkTCO Comp Training Enable/Disable ClkTCO Comp Training $EN_DIS **/ UINT8 CLKTCO; -/** Offset 0x0B17 - CMD Slew Rate Training +/** Offset 0x0B1F - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS **/ UINT8 CMDSR; -/** Offset 0x0B18 - Reserved +/** Offset 0x0B20 - Reserved **/ UINT8 Reserved56[2]; -/** Offset 0x0B1A - DIMM CA ODT Training +/** Offset 0x0B22 - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training $EN_DIS **/ UINT8 DIMMODTCA; -/** Offset 0x0B1B - Reserved +/** Offset 0x0B23 - Reserved **/ UINT8 Reserved57[3]; -/** Offset 0x0B1E - Read Vref Decap Training +/** Offset 0x0B26 - Read Vref Decap Training Enable/Disable Read Vref Decap Training $EN_DIS **/ UINT8 RDVREFDC; -/** Offset 0x0B1F - Vddq Training +/** Offset 0x0B27 - Vddq Training Enable/Disable Vddq Training $EN_DIS **/ UINT8 VDDQT; -/** Offset 0x0B20 - Rank Margin Tool Per Bit +/** Offset 0x0B28 - Rank Margin Tool Per Bit Enable/Disable Rank Margin Tool Per Bit $EN_DIS **/ UINT8 RMTBIT; -/** Offset 0x0B21 - Reserved +/** Offset 0x0B29 - Reserved **/ UINT8 Reserved58[4]; -/** Offset 0x0B25 - Duty Cycle Correction Training +/** Offset 0x0B2D - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training $EN_DIS **/ UINT8 DCC; -/** Offset 0x0B26 - Reserved +/** Offset 0x0B2E - Reserved **/ UINT8 Reserved59[17]; -/** Offset 0x0B37 - ECC Support +/** Offset 0x0B3F - ECC Support Enables/Disable ECC Support $EN_DIS **/ UINT8 EccSupport; -/** Offset 0x0B38 - Ibecc +/** Offset 0x0B40 - Ibecc In-Band ECC Support $EN_DIS **/ UINT8 Ibecc; -/** Offset 0x0B39 - IbeccParity +/** Offset 0x0B41 - IbeccParity In-Band ECC Parity Control $EN_DIS **/ UINT8 IbeccParity; -/** Offset 0x0B3A - IbeccOperationMode +/** Offset 0x0B42 - IbeccOperationMode In-Band ECC Operation Mode 0:Protect base on address range, 1: Non-protected, 2: All protected **/ UINT8 IbeccOperationMode; -/** Offset 0x0B3B - IbeccProtectedRegionEnable +/** Offset 0x0B43 - IbeccProtectedRegionEnable In-Band ECC Protected Region Enable $EN_DIS **/ UINT8 IbeccProtectedRegionEnable[8]; -/** Offset 0x0B43 - Reserved +/** Offset 0x0B4B - Reserved **/ UINT8 Reserved60; -/** Offset 0x0B44 - IbeccProtectedRegionBases +/** Offset 0x0B4C - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance **/ UINT16 IbeccProtectedRegionBase[8]; -/** Offset 0x0B54 - IbeccProtectedRegionMasks +/** Offset 0x0B5C - IbeccProtectedRegionMasks IBECC Protected Region Masks **/ UINT16 IbeccProtectedRegionMask[8]; -/** Offset 0x0B64 - IbeccProtectedRegionOverallBases +/** Offset 0x0B6C - IbeccProtectedRegionOverallBases IBECC Protected Region Bases based on enabled IBECC instance **/ UINT16 IbeccProtectedRegionOverallBase[8]; -/** Offset 0x0B74 - Memory Remap +/** Offset 0x0B7C - Memory Remap Enables/Disable Memory Remap $EN_DIS **/ UINT8 RemapEnable; -/** Offset 0x0B75 - Rank Interleave support +/** Offset 0x0B7D - Rank Interleave support Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time. $EN_DIS **/ UINT8 RankInterleave; -/** Offset 0x0B76 - Enhanced Interleave support +/** Offset 0x0B7E - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS **/ UINT8 EnhancedInterleave; -/** Offset 0x0B77 - Ch Hash Support +/** Offset 0x0B7F - Ch Hash Support Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ UINT8 ChHashEnable; -/** Offset 0x0B78 - Extern Therm Status +/** Offset 0x0B80 - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS **/ UINT8 EnableExtts; -/** Offset 0x0B79 - DDR PowerDown and idle counter +/** Offset 0x0B81 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDn; -/** Offset 0x0B7A - DDR PowerDown and idle counter +/** Offset 0x0B82 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDnLpddr; -/** Offset 0x0B7B - SelfRefresh Enable +/** Offset 0x0B83 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS **/ UINT8 SrefCfgEna; -/** Offset 0x0B7C - Throttler CKEMin Defeature +/** Offset 0x0B84 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS **/ UINT8 ThrtCkeMinDefeatLpddr; -/** Offset 0x0B7D - Throttler CKEMin Defeature +/** Offset 0x0B85 - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x0B7E - Reserved +/** Offset 0x0B86 - Reserved **/ UINT8 Reserved61; -/** Offset 0x0B7F - Exit On Failure (MRC) +/** Offset 0x0B87 - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS **/ UINT8 ExitOnFailure; -/** Offset 0x0B80 - Reserved +/** Offset 0x0B88 - Reserved **/ UINT8 Reserved62[4]; -/** Offset 0x0B84 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x0B8C - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedZq; -/** Offset 0x0B85 - Ch Hash Interleaved Bit +/** Offset 0x0B8D - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 **/ UINT8 ChHashInterleaveBit; -/** Offset 0x0B86 - Ch Hash Mask +/** Offset 0x0B8E - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0B88 - Base reference clock value +/** Offset 0x0B90 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz **/ UINT32 BClkFrequency; -/** Offset 0x0B8C - EPG DIMM Idd3N +/** Offset 0x0B94 - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26 **/ UINT16 Idd3n; -/** Offset 0x0B8E - EPG DIMM Idd3P +/** Offset 0x0B96 - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11 **/ UINT16 Idd3p; -/** Offset 0x0B90 - CMD Normalization +/** Offset 0x0B98 - CMD Normalization Enable/Disable CMD Normalization $EN_DIS **/ UINT8 CMDNORM; -/** Offset 0x0B91 - Early DQ Write Drive Strength and Equalization Training +/** Offset 0x0B99 - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive Strength and Equalization Training $EN_DIS **/ UINT8 EWRDSEQ; -/** Offset 0x0B92 - Idle Energy Mc0Ch0Dimm0 +/** Offset 0x0B9A - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc0Ch0Dimm0; -/** Offset 0x0B93 - Idle Energy Mc0Ch0Dimm1 +/** Offset 0x0B9B - Idle Energy Mc0Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc0Ch0Dimm1; -/** Offset 0x0B94 - Idle Energy Mc0Ch1Dimm0 +/** Offset 0x0B9C - Idle Energy Mc0Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc0Ch1Dimm0; -/** Offset 0x0B95 - Idle Energy Mc0Ch1Dimm1 +/** Offset 0x0B9D - Idle Energy Mc0Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc0Ch1Dimm1; -/** Offset 0x0B96 - Idle Energy Mc1Ch0Dimm0 +/** Offset 0x0B9E - Idle Energy Mc1Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc1Ch0Dimm0; -/** Offset 0x0B97 - Idle Energy Mc1Ch0Dimm1 +/** Offset 0x0B9F - Idle Energy Mc1Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc1Ch0Dimm1; -/** Offset 0x0B98 - Idle Energy Mc1Ch1Dimm0 +/** Offset 0x0BA0 - Idle Energy Mc1Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc1Ch1Dimm0; -/** Offset 0x0B99 - Idle Energy Mc1Ch1Dimm1 +/** Offset 0x0BA1 - Idle Energy Mc1Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyMc1Ch1Dimm1; -/** Offset 0x0B9A - PowerDown Energy Mc0Ch0Dimm0 +/** Offset 0x0BA2 - PowerDown Energy Mc0Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc0Ch0Dimm0; -/** Offset 0x0B9B - PowerDown Energy Mc0Ch0Dimm1 +/** Offset 0x0BA3 - PowerDown Energy Mc0Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc0Ch0Dimm1; -/** Offset 0x0B9C - PowerDown Energy Mc0Ch1Dimm0 +/** Offset 0x0BA4 - PowerDown Energy Mc0Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc0Ch1Dimm0; -/** Offset 0x0B9D - PowerDown Energy Mc0Ch1Dimm1 +/** Offset 0x0BA5 - PowerDown Energy Mc0Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc0Ch1Dimm1; -/** Offset 0x0B9E - PowerDown Energy Mc1Ch0Dimm0 +/** Offset 0x0BA6 - PowerDown Energy Mc1Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc1Ch0Dimm0; -/** Offset 0x0B9F - PowerDown Energy Mc1Ch0Dimm1 +/** Offset 0x0BA7 - PowerDown Energy Mc1Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc1Ch0Dimm1; -/** Offset 0x0BA0 - PowerDown Energy Mc1Ch1Dimm0 +/** Offset 0x0BA8 - PowerDown Energy Mc1Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc1Ch1Dimm0; -/** Offset 0x0BA1 - PowerDown Energy Mc1Ch1Dimm1 +/** Offset 0x0BA9 - PowerDown Energy Mc1Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) **/ UINT8 PdEnergyMc1Ch1Dimm1; -/** Offset 0x0BA2 - Activate Energy Mc0Ch0Dimm0 +/** Offset 0x0BAA - Activate Energy Mc0Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc0Ch0Dimm0; -/** Offset 0x0BA3 - Activate Energy Mc0Ch0Dimm1 +/** Offset 0x0BAB - Activate Energy Mc0Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc0Ch0Dimm1; -/** Offset 0x0BA4 - Activate Energy Mc0Ch1Dimm0 +/** Offset 0x0BAC - Activate Energy Mc0Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc0Ch1Dimm0; -/** Offset 0x0BA5 - Activate Energy Mc0Ch1Dimm1 +/** Offset 0x0BAD - Activate Energy Mc0Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc0Ch1Dimm1; -/** Offset 0x0BA6 - Activate Energy Mc1Ch0Dimm0 +/** Offset 0x0BAE - Activate Energy Mc1Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc1Ch0Dimm0; -/** Offset 0x0BA7 - Activate Energy Mc1Ch0Dimm1 +/** Offset 0x0BAF - Activate Energy Mc1Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc1Ch0Dimm1; -/** Offset 0x0BA8 - Activate Energy Mc1Ch1Dimm0 +/** Offset 0x0BB0 - Activate Energy Mc1Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc1Ch1Dimm0; -/** Offset 0x0BA9 - Activate Energy Mc1Ch1Dimm1 +/** Offset 0x0BB1 - Activate Energy Mc1Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyMc1Ch1Dimm1; -/** Offset 0x0BAA - Read Energy Mc0Ch0Dimm0 +/** Offset 0x0BB2 - Read Energy Mc0Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc0Ch0Dimm0; -/** Offset 0x0BAB - Read Energy Mc0Ch0Dimm1 +/** Offset 0x0BB3 - Read Energy Mc0Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc0Ch0Dimm1; -/** Offset 0x0BAC - Read Energy Mc0Ch1Dimm0 +/** Offset 0x0BB4 - Read Energy Mc0Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc0Ch1Dimm0; -/** Offset 0x0BAD - Read Energy Mc0Ch1Dimm1 +/** Offset 0x0BB5 - Read Energy Mc0Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc0Ch1Dimm1; -/** Offset 0x0BAE - Read Energy Mc1Ch0Dimm0 +/** Offset 0x0BB6 - Read Energy Mc1Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc1Ch0Dimm0; -/** Offset 0x0BAF - Read Energy Mc1Ch0Dimm1 +/** Offset 0x0BB7 - Read Energy Mc1Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc1Ch0Dimm1; -/** Offset 0x0BB0 - Read Energy Mc1Ch1Dimm0 +/** Offset 0x0BB8 - Read Energy Mc1Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc1Ch1Dimm0; -/** Offset 0x0BB1 - Read Energy Mc1Ch1Dimm1 +/** Offset 0x0BB9 - Read Energy Mc1Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyMc1Ch1Dimm1; -/** Offset 0x0BB2 - Write Energy Mc0Ch0Dimm0 +/** Offset 0x0BBA - Write Energy Mc0Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc0Ch0Dimm0; -/** Offset 0x0BB3 - Write Energy Mc0Ch0Dimm1 +/** Offset 0x0BBB - Write Energy Mc0Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc0Ch0Dimm1; -/** Offset 0x0BB4 - Write Energy Mc0Ch1Dimm0 +/** Offset 0x0BBC - Write Energy Mc0Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc0Ch1Dimm0; -/** Offset 0x0BB5 - Write Energy Mc0Ch1Dimm1 +/** Offset 0x0BBD - Write Energy Mc0Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc0Ch1Dimm1; -/** Offset 0x0BB6 - Write Energy Mc1Ch0Dimm0 +/** Offset 0x0BBE - Write Energy Mc1Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc1Ch0Dimm0; -/** Offset 0x0BB7 - Write Energy Mc1Ch0Dimm1 +/** Offset 0x0BBF - Write Energy Mc1Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc1Ch0Dimm1; -/** Offset 0x0BB8 - Write Energy Mc1Ch1Dimm0 +/** Offset 0x0BC0 - Write Energy Mc1Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc1Ch1Dimm0; -/** Offset 0x0BB9 - Write Energy Mc1Ch1Dimm1 +/** Offset 0x0BC1 - Write Energy Mc1Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyMc1Ch1Dimm1; -/** Offset 0x0BBA - Throttler CKEMin Timer +/** Offset 0x0BC2 - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Dfault is 0x00 **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x0BBB - Reserved +/** Offset 0x0BC3 - Reserved **/ UINT8 Reserved63[2]; -/** Offset 0x0BBD - Rapl Power Floor Ch0 +/** Offset 0x0BC5 - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh0; -/** Offset 0x0BBE - Rapl Power Floor Ch1 +/** Offset 0x0BC6 - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh1; -/** Offset 0x0BBF - Command Rate Support +/** Offset 0x0BC7 - Command Rate Support CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS **/ UINT8 EnCmdRate; -/** Offset 0x0BC0 - Reserved +/** Offset 0x0BC8 - Reserved **/ UINT8 Reserved64; -/** Offset 0x0BC1 - Energy Performance Gain +/** Offset 0x0BC9 - Energy Performance Gain Enable/disable Energy Performance Gain. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EpgEnable; -/** Offset 0x0BC2 - Reserved +/** Offset 0x0BCA - Reserved **/ UINT8 Reserved65; -/** Offset 0x0BC3 - User Manual Threshold +/** Offset 0x0BCB - User Manual Threshold Disabled: Predefined threshold will be used.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserThresholdEnable; -/** Offset 0x0BC4 - User Manual Budget +/** Offset 0x0BCC - User Manual Budget Disabled: Configuration of memories will defined the Budget value.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserBudgetEnable; -/** Offset 0x0BC5 - Reserved +/** Offset 0x0BCD - Reserved **/ UINT8 Reserved66; -/** Offset 0x0BC6 - Power Down Mode +/** Offset 0x0BCE - Power Down Mode This option controls command bus tristating during idle periods 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto **/ UINT8 PowerDownMode; -/** Offset 0x0BC7 - Pwr Down Idle Timer +/** Offset 0x0BCF - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo **/ UINT8 PwdwnIdleCounter; -/** Offset 0x0BC8 - Page Close Idle Timeout +/** Offset 0x0BD0 - Page Close Idle Timeout This option controls Page Close Idle Timeout 0:Enabled, 1:Disabled **/ UINT8 DisPgCloseIdleTimeout; -/** Offset 0x0BC9 - Bitmask of ranks that have CA bus terminated +/** Offset 0x0BD1 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating **/ UINT8 CmdRanksTerminated; -/** Offset 0x0BCA - PcdSerialDebugLevel +/** Offset 0x0BD2 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -2704,76 +2704,76 @@ **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0BCB - Reserved +/** Offset 0x0BD3 - Reserved **/ UINT8 Reserved67[8]; -/** Offset 0x0BD3 - Ask MRC to clear memory content +/** Offset 0x0BDB - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. $EN_DIS **/ UINT8 CleanMemory; -/** Offset 0x0BD4 - TCSS USB Port Enable +/** Offset 0x0BDC - TCSS USB Port Enable Bitmap for per port enabling **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x0BD5 - Reserved +/** Offset 0x0BDD - Reserved **/ UINT8 Reserved68; -/** Offset 0x0BD6 - Post Code Output Port +/** Offset 0x0BDE - Post Code Output Port This option configures Post Code Output Port **/ UINT16 PostCodeOutputPort; -/** Offset 0x0BD8 - RMTLoopCount +/** Offset 0x0BE0 - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO **/ UINT8 RMTLoopCount; -/** Offset 0x0BD9 - Enable/Disable SA CRID +/** Offset 0x0BE1 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS **/ UINT8 CridEnable; -/** Offset 0x0BDA - Reserved +/** Offset 0x0BE2 - Reserved **/ UINT8 Reserved69[2]; -/** Offset 0x0BDC - BCLK RFI Frequency +/** Offset 0x0BE4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No RFI Tuning. Range is 98Mhz-100Mhz. **/ UINT32 BclkRfiFreq[4]; -/** Offset 0x0BEC - Size of PCIe IMR. +/** Offset 0x0BF4 - Size of PCIe IMR. Size of PCIe IMR in megabytes **/ UINT16 PcieImrSize; -/** Offset 0x0BEE - Enable PCIe IMR +/** Offset 0x0BF6 - Enable PCIe IMR 0: Disable(AUTO), 1: Enable $EN_DIS **/ UINT8 PcieImrEnabled; -/** Offset 0x0BEF - Enable PCIe IMR +/** Offset 0x0BF7 - Enable PCIe IMR 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or SA PCIe $EN_DIS **/ UINT8 PcieImrRpLocation; -/** Offset 0x0BF0 - Root port number for IMR. +/** Offset 0x0BF8 - Root port number for IMR. Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 **/ UINT8 PcieImrRpSelection; -/** Offset 0x0BF1 - SerialDebugMrcLevel +/** Offset 0x0BF9 - SerialDebugMrcLevel MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -2782,214 +2782,214 @@ **/ UINT8 SerialDebugMrcLevel; -/** Offset 0x0BF2 - Reserved +/** Offset 0x0BFA - Reserved **/ UINT8 Reserved70[13]; -/** Offset 0x0BFF - Command Pins Mapping +/** Offset 0x0C07 - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. **/ UINT8 Lp5CccConfig; -/** Offset 0x0C00 - Command Pins Mirrored +/** Offset 0x0C08 - Command Pins Mirrored BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. **/ UINT8 CmdMirror; -/** Offset 0x0C01 - Reserved +/** Offset 0x0C09 - Reserved **/ UINT8 Reserved71[4]; -/** Offset 0x0C05 - Skip external display device scanning +/** Offset 0x0C0D - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0C06 - Generate BIOS Data ACPI Table +/** Offset 0x0C0E - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it $EN_DIS **/ UINT8 BdatEnable; -/** Offset 0x0C07 - Lock PCU Thermal Management registers +/** Offset 0x0C0F - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x0C08 - Panel Power Enable +/** Offset 0x0C10 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 PanelPowerEnable; -/** Offset 0x0C09 - BdatTestType +/** Offset 0x0C11 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D **/ UINT8 BdatTestType; -/** Offset 0x0C0A - Reserved +/** Offset 0x0C12 - Reserved **/ UINT8 Reserved72[2]; -/** Offset 0x0C0C - PMR Size +/** Offset 0x0C14 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot **/ UINT32 DmaBufferSize; -/** Offset 0x0C10 - The policy for VTd driver behavior +/** Offset 0x0C18 - The policy for VTd driver behavior BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS **/ UINT8 PreBootDmaMask; -/** Offset 0x0C11 - Reserved +/** Offset 0x0C19 - Reserved **/ UINT8 Reserved73[95]; -/** Offset 0x0C70 - TotalFlashSize +/** Offset 0x0C78 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable **/ UINT16 TotalFlashSize; -/** Offset 0x0C72 - BiosSize +/** Offset 0x0C7A - BiosSize The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected Range) so that a BIOS Update Script can be stored in the DPR. **/ UINT16 BiosSize; -/** Offset 0x0C74 - Reserved +/** Offset 0x0C7C - Reserved **/ UINT8 Reserved74[12]; -/** Offset 0x0C80 - Smbus dynamic power gating +/** Offset 0x0C88 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x0C81 - Disable and Lock Watch Dog Register +/** Offset 0x0C89 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x0C82 - Reserved +/** Offset 0x0C8A - Reserved **/ UINT8 Reserved75[2]; -/** Offset 0x0C84 - SMBUS SPD Write Disable +/** Offset 0x0C8C - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x0C85 - Reserved +/** Offset 0x0C8D - Reserved **/ UINT8 Reserved76[34]; -/** Offset 0x0CA7 - HECI Timeouts +/** Offset 0x0CAF - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS **/ UINT8 HeciTimeouts; -/** Offset 0x0CA8 - Force ME DID Init Status +/** Offset 0x0CB0 - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x0CA9 - CPU Replaced Polling Disable +/** Offset 0x0CB1 - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x0CAA - Check HECI message before send +/** Offset 0x0CB2 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x0CAB - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. +/** Offset 0x0CB3 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x0CAC - HECI2 Interface Communication +/** Offset 0x0CB4 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x0CAD - Enable KT device +/** Offset 0x0CB5 - Enable KT device Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x0CAE - Skip CPU replacement check +/** Offset 0x0CB6 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0CAF - Avx2 Voltage Guardband Scaling Factor +/** Offset 0x0CB7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx2VoltageScaleFactor; -/** Offset 0x0CB0 - Avx512 Voltage Guardband Scaling Factor +/** Offset 0x0CB8 - Avx512 Voltage Guardband Scaling Factor AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. **/ UINT8 Avx512VoltageScaleFactor; -/** Offset 0x0CB1 - Serial Io Uart Debug Mode +/** Offset 0x0CB9 - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x0CB2 - Reserved +/** Offset 0x0CBA - Reserved **/ UINT8 Reserved77[2]; -/** Offset 0x0CB4 - SerialIoUartDebugRxPinMux - FSPM +/** Offset 0x0CBC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug **/ UINT32 SerialIoUartDebugRxPinMux; -/** Offset 0x0CB8 - SerialIoUartDebugTxPinMux - FSPM +/** Offset 0x0CC0 - SerialIoUartDebugTxPinMux - FSPM Select TX pin muxing for SerialIo UART used for debug **/ UINT32 SerialIoUartDebugTxPinMux; -/** Offset 0x0CBC - SerialIoUartDebugRtsPinMux - FSPM +/** Offset 0x0CC4 - SerialIoUartDebugRtsPinMux - FSPM Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* for possible values. **/ UINT32 SerialIoUartDebugRtsPinMux; -/** Offset 0x0CC0 - SerialIoUartDebugCtsPinMux - FSPM +/** Offset 0x0CC8 - SerialIoUartDebugCtsPinMux - FSPM Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* for possible values. **/ UINT32 SerialIoUartDebugCtsPinMux; -/** Offset 0x0CC4 - Reserved +/** Offset 0x0CCC - Reserved **/ UINT8 Reserved78[172]; } FSP_M_CONFIG; @@ -3010,11 +3010,11 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0D70 +/** Offset 0x0D78 **/ UINT8 Rsvd500[6]; -/** Offset 0x0D76 +/** Offset 0x0D7E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h index f56b95b..e37e0dd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h @@ -685,10 +685,9 @@ **/ UINT8 PciePtm[29]; -/** Offset 0x0491 - PCIe DPC enable/disable - Enable/disable Downstream Port Containment for PCIE Root Ports. +/** Offset 0x0491 - Reserved **/ - UINT8 PcieDpc[29]; + UINT8 Reserved13[29]; /** Offset 0x04AE - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming @@ -699,7 +698,7 @@ /** Offset 0x04AF - Reserved **/ - UINT8 Reserved13[5]; + UINT8 Reserved14[5]; /** Offset 0x04B4 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will @@ -709,7 +708,7 @@ /** Offset 0x04B8 - Reserved **/ - UINT8 Reserved14; + UINT8 Reserved15; /** Offset 0x04B9 - PCH eSPI Link Configuration Lock (SBLCL) Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target @@ -750,7 +749,7 @@ /** Offset 0x04C1 - Reserved **/ - UINT8 Reserved15; + UINT8 Reserved16; /** Offset 0x04C2 - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 @@ -812,7 +811,7 @@ /** Offset 0x04CF - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved17; /** Offset 0x04D0 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. @@ -826,500 +825,500 @@ /** Offset 0x04D8 - Reserved **/ - UINT8 Reserved17[8]; + UINT8 Reserved18[16]; -/** Offset 0x04E0 - FIVR Dynamic Power Management +/** Offset 0x04E8 - FIVR Dynamic Power Management Enable/Disable FIVR Dynamic Power Management. $EN_DIS **/ UINT8 PchFivrDynPm; -/** Offset 0x04E1 - Reserved +/** Offset 0x04E9 - Reserved **/ - UINT8 Reserved18; + UINT8 Reserved19; -/** Offset 0x04E2 - External V1P05 Icc Max Value +/** Offset 0x04EA - External V1P05 Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtV1p05RailIccMaximum; -/** Offset 0x04E4 - External Vnn Icc Max Value that will be used in S0ix/Sx states +/** Offset 0x04EC - External Vnn Icc Max Value that will be used in S0ix/Sx states Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtVnnRailIccMaximum; -/** Offset 0x04E6 - External Vnn Icc Max Value that will be used in Sx states +/** Offset 0x04EE - External Vnn Icc Max Value that will be used in Sx states Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting is 1mA and maximal possible value is 500mA **/ UINT16 PchFivrExtVnnRailSxIccMaximum; -/** Offset 0x04E8 - Reserved +/** Offset 0x04F0 - Reserved **/ - UINT8 Reserved19[14]; + UINT8 Reserved20[14]; -/** Offset 0x04F6 - CNVi Configuration +/** Offset 0x04FE - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x04F7 - CNVi Wi-Fi Core +/** Offset 0x04FF - CNVi Wi-Fi Core Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviWifiCore; -/** Offset 0x04F8 - CNVi BT Core +/** Offset 0x0500 - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x04F9 - CNVi BT Audio Offload +/** Offset 0x0501 - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x04FA - Reserved +/** Offset 0x0502 - Reserved **/ - UINT8 Reserved20[2]; + UINT8 Reserved21[2]; -/** Offset 0x04FC - CNVi RF_RESET pin muxing +/** Offset 0x0504 - CNVi RF_RESET pin muxing Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default) or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. **/ UINT32 CnviRfResetPinMux; -/** Offset 0x0500 - CNVi CLKREQ pin muxing +/** Offset 0x0508 - CNVi CLKREQ pin muxing Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default) or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in GpioPins*.h. **/ UINT32 CnviClkreqPinMux; -/** Offset 0x0504 - Enable Host C10 reporting through eSPI +/** Offset 0x050C - Enable Host C10 reporting through eSPI Enable/disable Host C10 reporting to Device via eSPI Virtual Wire. $EN_DIS **/ UINT8 PchEspiHostC10ReportEnable; -/** Offset 0x0505 - PCH USB2 PHY Power Gating enable +/** Offset 0x050D - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PmcUsb2PhySusPgEnable; -/** Offset 0x0506 - PCH USB OverCurrent mapping enable +/** Offset 0x050E - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x0507 - Espi Lgmr Memory Range decode +/** Offset 0x050F - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x0508 - External V1P05 Control Ramp Timer value +/** Offset 0x0510 - External V1P05 Control Ramp Timer value Hold off time to be used when changing the v1p05_ctrl for external bypass value in us **/ UINT8 PchFivrExtV1p05RailCtrlRampTmr; -/** Offset 0x0509 - External VNN Control Ramp Timer value +/** Offset 0x0511 - External VNN Control Ramp Timer value Hold off time to be used when changing the vnn_ctrl for external bypass value in us **/ UINT8 PchFivrExtVnnRailCtrlRampTmr; -/** Offset 0x050A - Set SATA DEVSLP GPIO Reset Config +/** Offset 0x0512 - Set SATA DEVSLP GPIO Reset Config Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlpResetConfig[8]; -/** Offset 0x0512 - PCHHOT# pin +/** Offset 0x051A - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x0513 - SATA LED +/** Offset 0x051B - SATA LED SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ UINT8 SataLedEnable; -/** Offset 0x0514 - VRAlert# Pin +/** Offset 0x051C - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x0515 - AMT Switch +/** Offset 0x051D - AMT Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS **/ UINT8 AmtEnabled; -/** Offset 0x0516 - WatchDog Timer Switch +/** Offset 0x051E - WatchDog Timer Switch Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 WatchDogEnabled; -/** Offset 0x0517 - PET Progress +/** Offset 0x051F - PET Progress Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 FwProgress; -/** Offset 0x0518 - SOL Switch +/** Offset 0x0520 - SOL Switch Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx. Setting is invalid if AmtEnabled is 0. $EN_DIS **/ UINT8 AmtSolEnabled; -/** Offset 0x0519 - Reserved +/** Offset 0x0521 - Reserved **/ - UINT8 Reserved21; + UINT8 Reserved22; -/** Offset 0x051A - OS Timer +/** Offset 0x0522 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerOs; -/** Offset 0x051C - BIOS Timer +/** Offset 0x0524 - BIOS Timer 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0. **/ UINT16 WatchDogTimerBios; -/** Offset 0x051E - PCH PCIe root port connection type +/** Offset 0x0526 - PCH PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 PcieRpSlotImplemented[29]; -/** Offset 0x053B - PCIE RP Access Control Services Extended Capability +/** Offset 0x0543 - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 PcieRpAcsEnabled[29]; -/** Offset 0x0558 - PCIE RP Clock Power Management +/** Offset 0x0560 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[29]; -/** Offset 0x0575 - Reserved +/** Offset 0x057D - Reserved **/ - UINT8 Reserved22[3]; + UINT8 Reserved23[3]; -/** Offset 0x0578 - PCIE RP Detect Timeout Ms +/** Offset 0x0580 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[29]; -/** Offset 0x05B2 - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x05BA - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x05B3 - V1p05-PHY supply external FET control +/** Offset 0x05BB - V1p05-PHY supply external FET control Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY supply. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcV1p05PhyExtFetControlEn; -/** Offset 0x05B4 - V1p05-IS supply external FET control +/** Offset 0x05BC - V1p05-IS supply external FET control Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcV1p05IsExtFetControlEn; -/** Offset 0x05B5 - Enable/Disable PavpEnable +/** Offset 0x05BD - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS **/ UINT8 PavpEnable; -/** Offset 0x05B6 - Enable/Disable PeiGraphicsPeimInit +/** Offset 0x05BE - Enable/Disable PeiGraphicsPeimInit Enable(Default): FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB. Disable: FSP will NOT initialize the framebuffer. $EN_DIS **/ UINT8 PeiGraphicsPeimInit; -/** Offset 0x05B7 - Enable D3 Hot in TCSS +/** Offset 0x05BF - Enable D3 Hot in TCSS This policy will enable/disable D3 hot support in IOM $EN_DIS **/ UINT8 D3HotEnable; -/** Offset 0x05B8 - Enable or disable GNA device +/** Offset 0x05C0 - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 GnaEnable; -/** Offset 0x05B9 - Reserved +/** Offset 0x05C1 - Reserved **/ - UINT8 Reserved23[3]; + UINT8 Reserved24[3]; -/** Offset 0x05BC - TypeC port GPIO setting +/** Offset 0x05C4 - TypeC port GPIO setting GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Mtl = MeteorLake) **/ UINT32 IomTypeCPortPadCfg[12]; -/** Offset 0x05EC - CPU USB3 Port Over Current Pin +/** Offset 0x05F4 - CPU USB3 Port Over Current Pin Describe the specific over current pin number of USBC Port N. **/ UINT8 CpuUsb3OverCurrentPin[8]; -/** Offset 0x05F4 - Enable D3 Cold in TCSS +/** Offset 0x05FC - Enable D3 Cold in TCSS This policy will enable/disable D3 cold support in IOM $EN_DIS **/ UINT8 D3ColdEnable; -/** Offset 0x05F5 - Enable/Disable PCIe tunneling for USB4 +/** Offset 0x05FD - Enable/Disable PCIe tunneling for USB4 Enable/Disable PCIe tunneling for USB4, default is enable $EN_DIS **/ UINT8 ITbtPcieTunnelingForUsb4; -/** Offset 0x05F6 - Enable/Disable SkipFspGop +/** Offset 0x05FE - Enable/Disable SkipFspGop Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver $EN_DIS **/ UINT8 SkipFspGop; -/** Offset 0x05F7 - Enable/Disable VPU Device +/** Offset 0x05FF - Enable/Disable VPU Device Enable(Default): Enable VPU Device, Disable: Disable VPU Device $EN_DIS **/ UINT8 VpuEnable; -/** Offset 0x05F8 - TC State in TCSS +/** Offset 0x0600 - TC State in TCSS This TC C-State Limit in IOM **/ UINT8 TcCstateLimit; -/** Offset 0x05F9 - Reserved +/** Offset 0x0601 - Reserved **/ - UINT8 Reserved24[3]; + UINT8 Reserved25[3]; -/** Offset 0x05FC - Intel Graphics VBT (Video BIOS Table) Size +/** Offset 0x0604 - Intel Graphics VBT (Video BIOS Table) Size Size of Internal Graphics VBT Image **/ UINT32 VbtSize; -/** Offset 0x0600 - Platform LID Status for LFP Displays. +/** Offset 0x0608 - Platform LID Status for LFP Displays. LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen. 0: LidClosed, 1: LidOpen **/ UINT8 LidStatus; -/** Offset 0x0601 - Reserved +/** Offset 0x0609 - Reserved **/ - UINT8 Reserved25[8]; + UINT8 Reserved26[8]; -/** Offset 0x0609 - Enable VMD controller +/** Offset 0x0611 - Enable VMD controller Enable/disable to VMD controller.0: Disable; 1: Enable(Default) $EN_DIS **/ UINT8 VmdEnable; -/** Offset 0x060A - Enable VMD Global Mapping +/** Offset 0x0612 - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable(Default); 1: Enable $EN_DIS **/ UINT8 VmdGlobalMapping; -/** Offset 0x060B - Map port under VMD +/** Offset 0x0613 - Map port under VMD Map/UnMap port under VMD $EN_DIS **/ UINT8 VmdPort[31]; -/** Offset 0x062A - Reserved +/** Offset 0x0632 - Reserved **/ - UINT8 Reserved26[31]; + UINT8 Reserved27[31]; -/** Offset 0x0649 - VMD Port Device +/** Offset 0x0651 - VMD Port Device VMD Root port device number. **/ UINT8 VmdPortDev[31]; -/** Offset 0x0668 - VMD Port Func +/** Offset 0x0670 - VMD Port Func VMD Root port function number. **/ UINT8 VmdPortFunc[31]; -/** Offset 0x0687 - Reserved +/** Offset 0x068F - Reserved **/ - UINT8 Reserved27; + UINT8 Reserved28; -/** Offset 0x0688 - VMD Variable +/** Offset 0x0690 - VMD Variable VMD Variable Pointer. **/ UINT32 VmdVariablePtr; -/** Offset 0x068C - Temporary CfgBar address for VMD +/** Offset 0x0694 - Temporary CfgBar address for VMD VMD Variable Pointer. **/ UINT32 VmdCfgBarBase; -/** Offset 0x0690 - Temporary MemBar1 address for VMD +/** Offset 0x0698 - Temporary MemBar1 address for VMD VMD Variable Pointer. **/ UINT32 VmdMemBar1Base; -/** Offset 0x0694 - Temporary MemBar2 address for VMD +/** Offset 0x069C - Temporary MemBar2 address for VMD VMD Variable Pointer. **/ UINT32 VmdMemBar2Base; -/** Offset 0x0698 - Reserved +/** Offset 0x06A0 - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved29; -/** Offset 0x0699 - Enable/Disable PMC-PD Solution +/** Offset 0x06A1 - Enable/Disable PMC-PD Solution This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution $EN_DIS **/ UINT8 PmcPdEnable; -/** Offset 0x069A - TCSS Aux Orientation Override Enable +/** Offset 0x06A2 - TCSS Aux Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssAuxOri; -/** Offset 0x069C - TCSS HSL Orientation Override Enable +/** Offset 0x06A4 - TCSS HSL Orientation Override Enable Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides **/ UINT16 TcssHslOri; -/** Offset 0x069E - USB override in IOM +/** Offset 0x06A6 - USB override in IOM This policy will enable/disable USB Connect override in IOM $EN_DIS **/ UINT8 UsbOverride; -/** Offset 0x069F - ITBT Root Port Enable +/** Offset 0x06A7 - ITBT Root Port Enable ITBT Root Port Enable, 0:Disable, 1:Enable 0:Disable, 1:Enable **/ UINT8 ITbtPcieRootPortEn[4]; -/** Offset 0x06A3 - TCSS USB Port Enable +/** Offset 0x06AB - TCSS USB Port Enable Bits 0, 1, ... max Type C port control enables **/ UINT8 UsbTcPortEn; -/** Offset 0x06A4 - ITBTForcePowerOn Timeout value +/** Offset 0x06AC - ITBTForcePowerOn Timeout value ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. 100 = 100 ms. **/ UINT16 ITbtForcePowerOnTimeoutInMs; -/** Offset 0x06A6 - ITbtConnectTopology Timeout value +/** Offset 0x06AE - ITbtConnectTopology Timeout value ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range is 0-10000. 100 = 100 ms. **/ UINT16 ITbtConnectTopologyTimeoutInMs; -/** Offset 0x06A8 - VCCST request for IOM +/** Offset 0x06B0 - VCCST request for IOM This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 $EN_DIS **/ UINT8 VccSt; -/** Offset 0x06A9 - Reserved +/** Offset 0x06B1 - Reserved **/ - UINT8 Reserved29; + UINT8 Reserved30; -/** Offset 0x06AA - ITBT DMA LTR +/** Offset 0x06B2 - ITBT DMA LTR TCSS DMA1, DMA2 LTR value **/ UINT16 ITbtDmaLtr[2]; -/** Offset 0x06AE - Reserved +/** Offset 0x06B6 - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved31; -/** Offset 0x06AF - Enable/Disable PTM +/** Offset 0x06B7 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports $EN_DIS **/ UINT8 PtmEnabled[4]; -/** Offset 0x06B3 - PCIE RP Ltr Enable +/** Offset 0x06BB - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 SaPcieItbtRpLtrEnable[4]; -/** Offset 0x06B7 - PCIE RP Snoop Latency Override Mode +/** Offset 0x06BF - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; -/** Offset 0x06BB - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x06C3 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x06BF - Reserved +/** Offset 0x06C7 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved32; -/** Offset 0x06C0 - PCIE RP Snoop Latency Override Value +/** Offset 0x06C8 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; -/** Offset 0x06C8 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x06D0 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; -/** Offset 0x06CC - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x06D4 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x06D0 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x06D8 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; -/** Offset 0x06D8 - Force LTR Override +/** Offset 0x06E0 - Force LTR Override Force LTR Override. **/ UINT8 SaPcieItbtRpForceLtrOverride[4]; -/** Offset 0x06DC - PCIE RP Ltr Config Lock +/** Offset 0x06E4 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 SaPcieItbtRpLtrConfigLock[4]; -/** Offset 0x06E0 - Enable or Disable TXT +/** Offset 0x06E8 - Enable or Disable TXT Enables utilization of additional hardware capabilities provided by Intel (R) Trusted Execution Technology. Changes require a full power cycle to take effect. 0: Disable, 1: Enable. @@ -1327,27 +1326,27 @@ **/ UINT8 TxtEnable; -/** Offset 0x06E1 - Reserved +/** Offset 0x06E9 - Reserved **/ - UINT8 Reserved32[3]; + UINT8 Reserved33[3]; -/** Offset 0x06E4 - CpuBistData +/** Offset 0x06EC - CpuBistData Pointer CPU BIST Data **/ UINT32 CpuBistData; -/** Offset 0x06E8 - CpuMpPpi +/** Offset 0x06F0 - CpuMpPpi Optional pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI. If not NULL, FSP will use the boot loader's implementation of multiprocessing. See section 5.1.4 of the FSP Integration Guide for more details. **/ UINT32 CpuMpPpi; -/** Offset 0x06EC - Reserved +/** Offset 0x06F4 - Reserved **/ - UINT8 Reserved33[4]; + UINT8 Reserved34[4]; -/** Offset 0x06F0 - PpinSupport to view Protected Processor Inventory Number +/** Offset 0x06F8 - PpinSupport to view Protected Processor Inventory Number PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn off this feature. When 'PPIN Enable Mode' is selected, this shows second option where feature can be enabled based on EOM (End of Manufacturing) flag or it is @@ -1356,711 +1355,712 @@ **/ UINT8 PpinSupport; -/** Offset 0x06F1 - Reserved +/** Offset 0x06F9 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved35; -/** Offset 0x06F2 - Smbios Type4 Max Speed Override +/** Offset 0x06FA - Smbios Type4 Max Speed Override Provide the option for platform to override the MaxSpeed field of Smbios Type 4. If this value is not zero, it dominates the field. **/ UINT16 SmbiosType4MaxSpeedOverride; -/** Offset 0x06F4 - Advanced Encryption Standard (AES) feature +/** Offset 0x06FC - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 AesEnable; -/** Offset 0x06F5 - AvxDisable +/** Offset 0x06FD - AvxDisable Enable/Disable the AVX and AVX2 Instructions 0: Enable, 1: Disable **/ UINT8 AvxDisable; -/** Offset 0x06F6 - Reserved +/** Offset 0x06FE - Reserved **/ - UINT8 Reserved35[58]; + UINT8 Reserved36[58]; -/** Offset 0x0730 - Enable Power Optimizer +/** Offset 0x0738 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x0731 - PCH Flash Protection Ranges Write Enble +/** Offset 0x0739 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x0736 - PCH Flash Protection Ranges Read Enble +/** Offset 0x073E - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x073B - Reserved +/** Offset 0x0743 - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved37; -/** Offset 0x073C - PCH Protect Range Limit +/** Offset 0x0744 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x0746 - PCH Protect Range Base +/** Offset 0x074E - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x0750 - Enable Pme +/** Offset 0x0758 - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x0751 - HD Audio Link Frequency +/** Offset 0x0759 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x0752 - Enable PCH ISH SPI Cs0 pins assigned +/** Offset 0x075A - Enable PCH ISH SPI Cs0 pins assigned Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiCs0Enable[1]; -/** Offset 0x0753 - Enable PCH Io Apic Entry 24-119 +/** Offset 0x075B - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x0754 - PCH Io Apic ID +/** Offset 0x075C - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x0755 - Enable PCH ISH SPI pins assigned +/** Offset 0x075D - Enable PCH ISH SPI pins assigned Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshSpiEnable[1]; -/** Offset 0x0756 - Enable PCH ISH UART pins assigned +/** Offset 0x075E - Enable PCH ISH UART pins assigned Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshUartEnable[2]; -/** Offset 0x0758 - Enable PCH ISH I2C pins assigned +/** Offset 0x0760 - Enable PCH ISH I2C pins assigned Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI2cEnable[3]; -/** Offset 0x075B - Enable PCH ISH I3C pins assigned +/** Offset 0x0763 - Enable PCH ISH I3C pins assigned Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshI3cEnable; -/** Offset 0x075C - Enable PCH ISH GP pins assigned +/** Offset 0x0764 - Enable PCH ISH GP pins assigned Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable. **/ UINT8 PchIshGpEnable[12]; -/** Offset 0x0768 - PCH ISH PDT Unlock Msg +/** Offset 0x0770 - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x0769 - Reserved +/** Offset 0x0771 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved38; -/** Offset 0x076A - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x0772 - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x076B - Enable LOCKDOWN BIOS LOCK +/** Offset 0x0773 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x076C - PCH Compatibility Revision ID +/** Offset 0x0774 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x076D - RTC BIOS Interface Lock +/** Offset 0x0775 - RTC BIOS Interface Lock Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed. $EN_DIS **/ UINT8 RtcBiosInterfaceLock; -/** Offset 0x076E - RTC Cmos Memory Lock +/** Offset 0x0776 - RTC Cmos Memory Lock Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 RtcMemoryLock; -/** Offset 0x076F - Enable PCIE RP HotPlug +/** Offset 0x0777 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[29]; -/** Offset 0x078C - Enable PCIE RP Pm Sci +/** Offset 0x0794 - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. + $EN_DIS **/ UINT8 PcieRpPmSci[29]; -/** Offset 0x07A9 - Enable PCIE RP Transmitter Half Swing +/** Offset 0x07B1 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[29]; -/** Offset 0x07C6 - Enable PCIE RP Clk Req Detect +/** Offset 0x07CE - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[29]; -/** Offset 0x07E3 - PCIE RP Advanced Error Report +/** Offset 0x07EB - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[29]; -/** Offset 0x0800 - PCIE RP Unsupported Request Report +/** Offset 0x0808 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[29]; -/** Offset 0x081D - PCIE RP Fatal Error Report +/** Offset 0x0825 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[29]; -/** Offset 0x083A - PCIE RP No Fatal Error Report +/** Offset 0x0842 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[29]; -/** Offset 0x0857 - PCIE RP Correctable Error Report +/** Offset 0x085F - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[29]; -/** Offset 0x0874 - PCIE RP System Error On Fatal Error +/** Offset 0x087C - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[29]; -/** Offset 0x0891 - PCIE RP System Error On Non Fatal Error +/** Offset 0x0899 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[29]; -/** Offset 0x08AE - PCIE RP System Error On Correctable Error +/** Offset 0x08B6 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[29]; -/** Offset 0x08CB - PCIE RP Max Payload - Max Payload Size supported, Default 64B, see enum PCH_PCIE_MAX_PAYLOAD. +/** Offset 0x08D3 - PCIE RP Max Payload + Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[29]; -/** Offset 0x08E8 - Touch Host Controller Assignment +/** Offset 0x08F0 - Touch Host Controller Assignment Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1 **/ UINT8 ThcAssignment[2]; -/** Offset 0x08EA - Reserved +/** Offset 0x08F2 - Reserved **/ - UINT8 Reserved38[122]; + UINT8 Reserved39[122]; -/** Offset 0x0964 - PCIE RP Pcie Speed +/** Offset 0x096C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[29]; -/** Offset 0x0981 - PCIE RP Physical Slot Number +/** Offset 0x0989 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[29]; -/** Offset 0x099E - PCIE RP Completion Timeout +/** Offset 0x09A6 - PCIE RP Completion Timeout The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[29]; -/** Offset 0x09BB - PCIE RP Aspm +/** Offset 0x09C3 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[29]; -/** Offset 0x09D8 - PCIE RP L1 Substates +/** Offset 0x09E0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[29]; -/** Offset 0x09F5 - PCIE RP Ltr Enable +/** Offset 0x09FD - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[29]; -/** Offset 0x0A12 - PCIE RP Ltr Config Lock +/** Offset 0x0A1A - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[29]; -/** Offset 0x0A2F - PCIE RP override default settings for EQ +/** Offset 0x0A37 - PCIE RP override default settings for EQ Choose PCIe EQ method $EN_DIS **/ UINT8 PcieEqOverrideDefault[29]; -/** Offset 0x0A4C - Reserved +/** Offset 0x0A54 - Reserved **/ - UINT8 Reserved39[3767]; + UINT8 Reserved40[3767]; -/** Offset 0x1903 - PCIE RP Enable Peer Memory Write +/** Offset 0x190B - PCIE RP Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite[12]; -/** Offset 0x190F - PCIE Compliance Test Mode +/** Offset 0x1917 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x1910 - PCIE Rp Function Swap +/** Offset 0x1918 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x1911 - Reserved +/** Offset 0x1919 - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved41; -/** Offset 0x1912 - PCH Pm PME_B0_S5_DIS +/** Offset 0x191A - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x1913 - PCIE IMR +/** Offset 0x191B - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x1914 - PCIE IMR port number +/** Offset 0x191C - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x1915 - PCH Pm Wol Enable Override +/** Offset 0x191D - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x1916 - PCH Pm WoW lan Enable +/** Offset 0x191E - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x1917 - Reserved +/** Offset 0x191F - Reserved **/ - UINT8 Reserved41[4]; + UINT8 Reserved42[4]; -/** Offset 0x191B - PCH Pm Slp S3 Min Assert +/** Offset 0x1923 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x191C - PCH Pm Slp S4 Min Assert +/** Offset 0x1924 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x191D - PCH Pm Slp Sus Min Assert +/** Offset 0x1925 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x191E - PCH Pm Slp A Min Assert +/** Offset 0x1926 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x191F - USB Overcurrent Override for VISA +/** Offset 0x1927 - USB Overcurrent Override for VISA This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when VISA pin is muxed with USB OC $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x1920 - PCH Pm Slp Strch Sus Up +/** Offset 0x1928 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x1921 - PCH Pm Slp Lan Low Dc +/** Offset 0x1929 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x1922 - PCH Pm Pwr Btn Override Period +/** Offset 0x192A - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x1923 - PCH Pm Disable Native Power Button +/** Offset 0x192B - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x1924 - PCH Pm ME_WAKE_STS +/** Offset 0x192C - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x1925 - PCH Pm WOL_OVR_WK_STS +/** Offset 0x192D - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x1926 - PCH Pm Reset Power Cycle Duration +/** Offset 0x192E - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x1927 - PCH Pm Pcie Pll Ssc +/** Offset 0x192F - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x1928 - PCH Legacy IO Low Latency Enable +/** Offset 0x1930 - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x1929 - PCH Sata Pwr Opt Enable +/** Offset 0x1931 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x192A - PCH Sata eSATA Speed Limit +/** Offset 0x1932 - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x192B - PCH Sata Speed Limit +/** Offset 0x1933 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x192C - Enable SATA Port HotPlug +/** Offset 0x1934 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x1934 - Enable SATA Port Interlock Sw +/** Offset 0x193C - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x193C - Enable SATA Port External +/** Offset 0x1944 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x1944 - Enable SATA Port SpinUp +/** Offset 0x194C - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x194C - Enable SATA Port Solid State Drive +/** Offset 0x1954 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x1954 - Enable SATA Port Enable Dito Config +/** Offset 0x195C - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x195C - Enable SATA Port DmVal +/** Offset 0x1964 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x1964 - Reserved +/** Offset 0x196C - Reserved **/ - UINT8 Reserved42[2]; + UINT8 Reserved43[2]; -/** Offset 0x1966 - Enable SATA Port DmVal +/** Offset 0x196E - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x1976 - Enable SATA Port ZpOdd +/** Offset 0x197E - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x197E - PCH Sata Rst Raid Alternate Id +/** Offset 0x1986 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. $EN_DIS **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x197F - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x1987 - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x1982 - PCH Sata Rst Pcie Storage Port +/** Offset 0x198A - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x1985 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x198D - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x1988 - UFS enable/disable +/** Offset 0x1990 - UFS enable/disable Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller 0 and (0,1) to enable controller 1 $EN_DIS **/ UINT8 UfsEnable[2]; -/** Offset 0x198A - Reserved +/** Offset 0x1992 - Reserved **/ - UINT8 Reserved43[2]; + UINT8 Reserved44[2]; -/** Offset 0x198C - IEH Mode +/** Offset 0x1994 - IEH Mode Integrated Error Handler Mode, 0: Bypass, 1: Enable 0: Bypass, 1:Enable **/ UINT8 IehMode; -/** Offset 0x198D - Reserved +/** Offset 0x1995 - Reserved **/ - UINT8 Reserved44[11]; + UINT8 Reserved45[11]; -/** Offset 0x1998 - PCH Thermal Throttling Custimized T0Level Value +/** Offset 0x19A0 - PCH Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x199A - PCH Thermal Throttling Custimized T1Level Value +/** Offset 0x19A2 - PCH Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x199C - PCH Thermal Throttling Custimized T2Level Value +/** Offset 0x19A4 - PCH Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x199E - Enable PCH Thermal Throttle +/** Offset 0x19A6 - Enable PCH Thermal Throttle Enable thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x199F - PCH PMSync State 13 +/** Offset 0x19A7 - PCH PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x19A0 - PCH Thermal Throttle Lock +/** Offset 0x19A8 - PCH Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x19A1 - Reserved +/** Offset 0x19A9 - Reserved **/ - UINT8 Reserved45[9]; + UINT8 Reserved46[9]; -/** Offset 0x19AA - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x19B2 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x19AB - DMI Thermal Sensor Suggested Setting +/** Offset 0x19B3 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x19AC - Thermal Sensor 0 Target Width +/** Offset 0x19B4 - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x19AD - Thermal Sensor 1 Target Width +/** Offset 0x19B5 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x19AE - Thermal Sensor 2 Target Width +/** Offset 0x19B6 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x19AF - Thermal Sensor 3 Target Width +/** Offset 0x19B7 - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x19B0 - Port 0 T1 Multipler +/** Offset 0x19B8 - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x19B1 - Port 0 T2 Multipler +/** Offset 0x19B9 - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x19B2 - Port 0 T3 Multipler +/** Offset 0x19BA - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x19B3 - Port 0 Tdispatch +/** Offset 0x19BB - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x19B4 - Port 1 T1 Multipler +/** Offset 0x19BC - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x19B5 - Port 1 T2 Multipler +/** Offset 0x19BD - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x19B6 - Port 1 T3 Multipler +/** Offset 0x19BE - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x19B7 - Port 1 Tdispatch +/** Offset 0x19BF - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x19B8 - Port 0 Tinactive +/** Offset 0x19C0 - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x19B9 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x19C1 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x19BA - Port 1 Tinactive +/** Offset 0x19C2 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x19BB - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x19C3 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x19BC - Sata Thermal Throttling Suggested Setting +/** Offset 0x19C4 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x19BD - Reserved +/** Offset 0x19C5 - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved47; -/** Offset 0x19BE - Thermal Device Temperature +/** Offset 0x19C6 - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x19C0 - USB2 Port Over Current Pin +/** Offset 0x19C8 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x19D0 - USB3 Port Over Current Pin +/** Offset 0x19D8 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x19DA - Enable xHCI LTR override +/** Offset 0x19E2 - Enable xHCI LTR override Enables override of recommended LTR values for xHCI $EN_DIS **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x19DB - Reserved +/** Offset 0x19E3 - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved48; -/** Offset 0x19DC - xHCI High Idle Time LTR override +/** Offset 0x19E4 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting **/ UINT32 PchUsbLtrHighIdleTimeOverride; -/** Offset 0x19E0 - xHCI Medium Idle Time LTR override +/** Offset 0x19E8 - xHCI Medium Idle Time LTR override Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting **/ UINT32 PchUsbLtrMediumIdleTimeOverride; -/** Offset 0x19E4 - xHCI Low Idle Time LTR override +/** Offset 0x19EC - xHCI Low Idle Time LTR override Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting **/ UINT32 PchUsbLtrLowIdleTimeOverride; -/** Offset 0x19E8 - Enable 8254 Static Clock Gating +/** Offset 0x19F0 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2068,7 +2068,7 @@ **/ UINT8 Enable8254ClockGating; -/** Offset 0x19E9 - Enable 8254 Static Clock Gating On S3 +/** Offset 0x19F1 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2076,7 +2076,7 @@ **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x19EA - Enable TCO timer. +/** Offset 0x19F2 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2084,102 +2084,102 @@ **/ UINT8 EnableTcoTimer; -/** Offset 0x19EB - Reserved +/** Offset 0x19F3 - Reserved **/ - UINT8 Reserved48[5]; + UINT8 Reserved49[5]; -/** Offset 0x19F0 - BgpdtHash[4] +/** Offset 0x19F8 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x1A10 - BiosGuardAttr +/** Offset 0x1A18 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x1A14 - Reserved +/** Offset 0x1A1C - Reserved **/ - UINT8 Reserved49[4]; + UINT8 Reserved50[4]; -/** Offset 0x1A18 - BiosGuardModulePtr +/** Offset 0x1A20 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x1A20 - SendEcCmd +/** Offset 0x1A28 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x1A28 - EcCmdProvisionEav +/** Offset 0x1A30 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x1A29 - EcCmdLock +/** Offset 0x1A31 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x1A2A - Reserved +/** Offset 0x1A32 - Reserved **/ - UINT8 Reserved50[22]; + UINT8 Reserved51[22]; -/** Offset 0x1A40 - Skip Ssid Programming. +/** Offset 0x1A48 - Skip Ssid Programming. When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. $EN_DIS **/ UINT8 SiSkipSsidProgramming; -/** Offset 0x1A41 - Reserved +/** Offset 0x1A49 - Reserved **/ - UINT8 Reserved51; + UINT8 Reserved52; -/** Offset 0x1A42 - Change Default SVID +/** Offset 0x1A4A - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSvid; -/** Offset 0x1A44 - Change Default SSID +/** Offset 0x1A4C - Change Default SSID Change the default SSID used in FSP to programming internal devices. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiCustomizedSsid; -/** Offset 0x1A46 - Reserved +/** Offset 0x1A4E - Reserved **/ - UINT8 Reserved52[2]; + UINT8 Reserved53[2]; -/** Offset 0x1A48 - SVID SDID table Poniter. +/** Offset 0x1A50 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is only valid when SkipSsidProgramming is FALSE. **/ UINT32 SiSsidTablePtr; -/** Offset 0x1A4C - Number of ssid table. +/** Offset 0x1A54 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. This is only valid when SkipSsidProgramming is FALSE. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x1A4E - USB2 Port Reset Message Enable +/** Offset 0x1A56 - USB2 Port Reset Message Enable 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must be enable for USB2 Port those are paired with CPU XHCI Port **/ UINT8 PortResetMessageEnable[16]; -/** Offset 0x1A5E - SATA RST Interrupt Mode +/** Offset 0x1A66 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x1A5F - Enable PS_ON. +/** Offset 0x1A67 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2187,114 +2187,114 @@ **/ UINT8 PsOnEnable; -/** Offset 0x1A60 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x1A68 - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x1A61 - Pch Dmi Aspm Ctrl +/** Offset 0x1A69 - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x1A62 - PchDmiCwbEnable +/** Offset 0x1A6A - PchDmiCwbEnable Central Write Buffer feature configurable and enabled by default $EN_DIS **/ UINT8 PchDmiCwbEnable; -/** Offset 0x1A63 - OS IDLE Mode Enable +/** Offset 0x1A6B - OS IDLE Mode Enable Enable/Disable OS Idle Mode $EN_DIS **/ UINT8 PmcOsIdleEnable; -/** Offset 0x1A64 - S0ix Auto-Demotion +/** Offset 0x1A6C - S0ix Auto-Demotion Enable/Disable the Low Power Mode Auto-Demotion Host Control feature. $EN_DIS **/ UINT8 PchS0ixAutoDemotion; -/** Offset 0x1A65 - Latch Events C10 Exit +/** Offset 0x1A6D - Latch Events C10 Exit When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) $EN_DIS **/ UINT8 PchPmLatchEventsC10Exit; -/** Offset 0x1A66 - Reserved +/** Offset 0x1A6E - Reserved **/ - UINT8 Reserved53[126]; + UINT8 Reserved54[127]; -/** Offset 0x1AE4 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 +/** Offset 0x1AED - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTranEnable[10]; -/** Offset 0x1AEE - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 +/** Offset 0x1AF7 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate3UniqTran[10]; -/** Offset 0x1AF8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 +/** Offset 0x1B01 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTranEnable[10]; -/** Offset 0x1B02 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 +/** Offset 0x1B0B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate2UniqTran[10]; -/** Offset 0x1B0C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 +/** Offset 0x1B15 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTranEnable[10]; -/** Offset 0x1B16 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 +/** Offset 0x1B1F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate1UniqTran[10]; -/** Offset 0x1B20 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 +/** Offset 0x1B29 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each value in array can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTranEnable[10]; -/** Offset 0x1B2A - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 +/** Offset 0x1B33 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], Default = 4Ch. One byte for each port. **/ UINT8 Usb3HsioTxRate0UniqTran[10]; -/** Offset 0x1B34 - Skip PAM regsiter lock +/** Offset 0x1B3D - Skip PAM regsiter lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x1B35 - Enable/Disable IGFX RenderStandby +/** Offset 0x1B3E - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x1B36 - Reserved +/** Offset 0x1B3F - Reserved **/ - UINT8 Reserved54; + UINT8 Reserved55; -/** Offset 0x1B37 - GT Frequency Limit +/** Offset 0x1B40 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2308,51 +2308,51 @@ **/ UINT8 GtFreqMax; -/** Offset 0x1B38 - Disable Turbo GT +/** Offset 0x1B41 - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x1B39 - Reserved +/** Offset 0x1B42 - Reserved **/ - UINT8 Reserved55[2]; + UINT8 Reserved56[2]; -/** Offset 0x1B3B - Enable TSN Multi-VC +/** Offset 0x1B44 - Enable TSN Multi-VC Enable/disable Multi Virtual Channels(VC) in TSN. $EN_DIS **/ UINT8 PchTsnMultiVcEnable; -/** Offset 0x1B3C - Reserved +/** Offset 0x1B45 - Reserved **/ - UINT8 Reserved56[12]; + UINT8 Reserved57[11]; -/** Offset 0x1B48 - LogoPixelHeight Address +/** Offset 0x1B50 - LogoPixelHeight Address Address of LogoPixelHeight **/ UINT32 LogoPixelHeight; -/** Offset 0x1B4C - LogoPixelWidth Address +/** Offset 0x1B54 - LogoPixelWidth Address Address of LogoPixelWidth **/ UINT32 LogoPixelWidth; -/** Offset 0x1B50 - Reserved +/** Offset 0x1B58 - Reserved **/ - UINT8 Reserved57[45]; + UINT8 Reserved58[45]; -/** Offset 0x1B7D - RSR feature +/** Offset 0x1B85 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableRsr; -/** Offset 0x1B7E - Reserved +/** Offset 0x1B86 - Reserved **/ - UINT8 Reserved58[4]; + UINT8 Reserved59[4]; -/** Offset 0x1B82 - Enable or Disable HWP +/** Offset 0x1B8A - Enable or Disable HWP Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; 1: Enable; @@ -2360,7 +2360,7 @@ **/ UINT8 Hwp; -/** Offset 0x1B83 - Package Long duration turbo mode time +/** Offset 0x1B8B - Package Long duration turbo mode time Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained. Valid values(Unit @@ -2369,14 +2369,14 @@ **/ UINT8 PowerLimit1Time; -/** Offset 0x1B84 - Short Duration Turbo Mode +/** Offset 0x1B8C - Short Duration Turbo Mode Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program the default values for Power Limit 2. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x1B85 - Turbo settings Lock +/** Offset 0x1B8D - Turbo settings Lock Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT MSR will be locked and a reset will be required to unlock the register. 0: Disable; 1: Enable @@ -2384,7 +2384,7 @@ **/ UINT8 TurboPowerLimitLock; -/** Offset 0x1B86 - Package PL3 time window +/** Offset 0x1B8E - Package PL3 time window Power Limit 3 Time Window value in Milli seconds. Indicates the time window over which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves the hardware default value. Valid value: 0, 3-8, 10, 12, 14, 16, 20, 24, @@ -2392,111 +2392,111 @@ **/ UINT8 PowerLimit3Time; -/** Offset 0x1B87 - Package PL3 Duty Cycle +/** Offset 0x1B8F - Package PL3 Duty Cycle Specify the duty cycle in percentage that the CPU is required to maintain over the configured time window. Range is 0-100. **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x1B88 - Package PL3 Lock +/** Offset 0x1B90 - Package PL3 Lock Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled PL3 configuration can be changed during OS. 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x1B89 - Package PL4 Lock +/** Offset 0x1B91 - Package PL4 Lock Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled PL4 configuration can be changed during OS. 0: Disable ; 1:Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x1B8A - TCC Activation Offset +/** Offset 0x1B92 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts. Default = 0h. **/ UINT8 TccActivationOffset; -/** Offset 0x1B8B - Tcc Offset Clamp Enable/Disable +/** Offset 0x1B93 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1. 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetClamp; -/** Offset 0x1B8C - Tcc Offset Lock +/** Offset 0x1B94 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x1B8D - Custom Ratio State Entries +/** Offset 0x1B95 - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table. Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x1B8E - Custom Short term Power Limit time window +/** Offset 0x1B96 - Custom Short term Power Limit time window Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained. **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x1B8F - Custom Turbo Activation Ratio +/** Offset 0x1B97 - Custom Turbo Activation Ratio Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x1B90 - Custom Config Tdp Control +/** Offset 0x1B98 - Custom Config Tdp Control Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x1B91 - Custom Short term Power Limit time window +/** Offset 0x1B99 - Custom Short term Power Limit time window Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained. **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x1B92 - Custom Turbo Activation Ratio +/** Offset 0x1B9A - Custom Turbo Activation Ratio Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x1B93 - Custom Config Tdp Control +/** Offset 0x1B9B - Custom Config Tdp Control Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x1B94 - Custom Short term Power Limit time window +/** Offset 0x1B9C - Custom Short term Power Limit time window Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default value (28 sec for Mobile and 8 sec for Desktop). Defines time window which Processor Base Power (TDP) value should be maintained. **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x1B95 - Custom Turbo Activation Ratio +/** Offset 0x1B9D - Custom Turbo Activation Ratio Custom value for Turbo Activation Ratio. Needs to be configured with valid values from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x1B96 - Custom Config Tdp Control +/** Offset 0x1B9E - Custom Config Tdp Control Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x1B97 - ConfigTdp mode settings Lock +/** Offset 0x1B9F - ConfigTdp mode settings Lock cTDP(Assured Power) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL. Note: When CTDP(Assured Power) Lock is enabled Custom ConfigTDP Count will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. 0: Disable; 1: Enable @@ -2504,14 +2504,14 @@ **/ UINT8 ConfigTdpLock; -/** Offset 0x1B98 - Load Configurable TDP SSDT +/** Offset 0x1BA0 - Load Configurable TDP SSDT Enables cTDP(Assured Power) control via runtime ACPI BIOS methods. This 'BIOS only' feature does not require EC or driver support. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x1B99 - PL1 Enable value +/** Offset 0x1BA1 - PL1 Enable value Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it activates the PL1 value to be used by the processor to limit the average power of given time window. 0: Disable; 1: Enable. @@ -2519,7 +2519,7 @@ **/ UINT8 PsysPowerLimit1; -/** Offset 0x1B9A - PL1 timewindow +/** Offset 0x1BA2 - PL1 timewindow Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0 = default values. Indicates the time window over which Platform Processor Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to @@ -2527,7 +2527,7 @@ **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x1B9B - PL2 Enable Value +/** Offset 0x1BA3 - PL2 Enable Value Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS will program the default values for Platform Power Limit 2. 0: Disable; 1: Enable. @@ -2535,57 +2535,57 @@ **/ UINT8 PsysPowerLimit2; -/** Offset 0x1B9C - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x1BA4 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x1B9D - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x1BA5 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x1B9E - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x1BA6 - Enable or Disable Monitor /MWAIT instructions Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner should not set in MWAIT Loop. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x1B9F - Enable or Disable initialization of machine check registers +/** Offset 0x1BA7 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x1BA0 - AP Idle Manner of waiting for SIPI +/** Offset 0x1BA8 - AP Idle Manner of waiting for SIPI AP threads Idle Manner for waiting signal to run. 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x1BA1 - Control on Processor Trace output scheme +/** Offset 0x1BA9 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x1BA2 - Enable or Disable Processor Trace feature +/** Offset 0x1BAA - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x1BA3 - Enable or Disable Intel SpeedStep Technology +/** Offset 0x1BAB - Enable or Disable Intel SpeedStep Technology Allows more than two frequency ranges to be supported. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x1BA4 - Enable or Disable Energy Efficient P-state +/** Offset 0x1BAC - Enable or Disable Energy Efficient P-state Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS @@ -2595,7 +2595,7 @@ **/ UINT8 EnergyEfficientPState; -/** Offset 0x1BA5 - Enable or Disable Energy Efficient Turbo +/** Offset 0x1BAD - Enable or Disable Energy Efficient Turbo Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically lower the turbo frequency to increase efficiency. Recommended only to disable in overclocking situations where turbo frequency must remain constant. Otherwise, @@ -2604,100 +2604,100 @@ **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x1BA6 - Enable or Disable T states +/** Offset 0x1BAE - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x1BA7 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x1BAF - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x1BA8 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x1BB0 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x1BA9 - Enable or Disable PROCHOT# Response +/** Offset 0x1BB1 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x1BAA - Enable or Disable VR Thermal Alert +/** Offset 0x1BB2 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x1BAB - Enable or Disable Thermal Reporting +/** Offset 0x1BB3 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 EnableAllThermalFunctions; -/** Offset 0x1BAC - Enable or Disable Thermal Monitor +/** Offset 0x1BB4 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x1BAD - Enable or Disable CPU power states (C-states) +/** Offset 0x1BB5 - Enable or Disable CPU power states (C-states) Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not 100% utilized. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x1BAE - Configure C-State Configuration Lock +/** Offset 0x1BB6 - Configure C-State Configuration Lock Configure MSR to CFG Lock bit. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x1BAF - Enable or Disable Enhanced C-states +/** Offset 0x1BB7 - Enable or Disable Enhanced C-states Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores enter C-State. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x1BB0 - Enable or Disable Package Cstate Demotion +/** Offset 0x1BB8 - Enable or Disable Package Cstate Demotion Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x1BB1 - Enable or Disable Package Cstate UnDemotion +/** Offset 0x1BB9 - Enable or Disable Package Cstate UnDemotion Enable or Disable Package C-State Un-Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x1BB2 - Enable or Disable CState-Pre wake +/** Offset 0x1BBA - Enable or Disable CState-Pre wake Disable - to disable the Cstate Pre-Wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x1BB3 - Enable or Disable TimedMwait Support. +/** Offset 0x1BBB - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x1BB4 - Enable or Disable IO to MWAIT redirection +/** Offset 0x1BBC - Enable or Disable IO to MWAIT redirection When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset to MWAIT(offset). 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x1BB5 - Set the Max Pkg Cstate +/** Offset 0x1BBD - Set the Max Pkg Cstate Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value. Auto: Initializes to deepest available Package C State Limit. Valid values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 - @@ -2705,38 +2705,38 @@ **/ UINT8 PkgCStateLimit; -/** Offset 0x1BB6 - Interrupt Redirection Mode Select +/** Offset 0x1BBE - Interrupt Redirection Mode Select Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1: Round robin; 2: Hash vector; 7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x1BB7 - Lock prochot configuration +/** Offset 0x1BBF - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x1BB8 - Configuration for boot TDP selection +/** Offset 0x1BC0 - Configuration for boot TDP selection cTDP(Assured Power) Mode as Nominal/Level1/Level2/Deactivate TDP(Base Power) selection. Deactivate option will set MSR to Nominal and MMIO to Zero. 0: TDP(Base Power) Nominal; 1: TDP(Base Power) Down; 2: TDP(Base Power) Up;0xFF : Deactivate **/ UINT8 ConfigTdpLevel; -/** Offset 0x1BB9 - Max P-State Ratio +/** Offset 0x1BC1 - Max P-State Ratio Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x1BBA - P-state ratios for custom P-state table +/** Offset 0x1BC2 - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x1BE2 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x1BEA - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -2745,11 +2745,11 @@ **/ UINT8 StateRatioMax16[16]; -/** Offset 0x1BF2 - Reserved +/** Offset 0x1BFA - Reserved **/ - UINT8 Reserved59[2]; + UINT8 Reserved60[2]; -/** Offset 0x1BF4 - Package Long duration turbo mode power limit +/** Offset 0x1BFC - Package Long duration turbo mode power limit Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit @@ -2759,7 +2759,7 @@ **/ UINT32 PowerLimit1; -/** Offset 0x1BF8 - Package Short duration turbo mode power limit +/** Offset 0x1C00 - Package Short duration turbo mode power limit Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor Base Power (TDP). Processor applies control policies such that the package power @@ -2768,7 +2768,7 @@ **/ UINT32 PowerLimit2Power; -/** Offset 0x1BFC - Package PL3 power limit +/** Offset 0x1C04 - Package PL3 power limit Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between @@ -2778,22 +2778,22 @@ **/ UINT32 PowerLimit3; -/** Offset 0x1C00 - Package PL4 power limit +/** Offset 0x1C08 - Package PL4 power limit Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767. **/ UINT32 PowerLimit4; -/** Offset 0x1C04 - Reserved +/** Offset 0x1C0C - Reserved **/ - UINT8 Reserved60[4]; + UINT8 Reserved61[4]; -/** Offset 0x1C08 - Tcc Offset Time Window for RATL +/** Offset 0x1C10 - Tcc Offset Time Window for RATL **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x1C0C - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x1C14 - Short term Power Limit value for custom cTDP level 1 Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit @@ -2802,7 +2802,7 @@ **/ UINT32 Custom1PowerLimit1; -/** Offset 0x1C10 - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x1C18 - Long term Power Limit value for custom cTDP level 1 Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -2810,7 +2810,7 @@ **/ UINT32 Custom1PowerLimit2; -/** Offset 0x1C14 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x1C1C - Short term Power Limit value for custom cTDP level 2 Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit @@ -2819,7 +2819,7 @@ **/ UINT32 Custom2PowerLimit1; -/** Offset 0x1C18 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x1C20 - Long term Power Limit value for custom cTDP level 2 Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -2827,7 +2827,7 @@ **/ UINT32 Custom2PowerLimit2; -/** Offset 0x1C1C - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x1C24 - Short term Power Limit value for custom cTDP level 3 Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit @@ -2836,7 +2836,7 @@ **/ UINT32 Custom3PowerLimit1; -/** Offset 0x1C20 - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x1C28 - Long term Power Limit value for custom cTDP level 3 Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. 0 = no custom override. Processor applies control policies such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -2844,7 +2844,7 @@ **/ UINT32 Custom3PowerLimit2; -/** Offset 0x1C24 - Platform PL1 power +/** Offset 0x1C2C - Platform PL1 power Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. Any value can be programmed between Max and Min Power Limits. This setting will act as the new PL1 value for the Package @@ -2853,7 +2853,7 @@ **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x1C28 - Platform PL2 power +/** Offset 0x1C30 - Platform PL2 power Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W when programming. Value set 120 = 15W. Any value can be programmed between Max and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value @@ -2862,11 +2862,11 @@ **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x1C2C - Reserved +/** Offset 0x1C34 - Reserved **/ - UINT8 Reserved61; + UINT8 Reserved62; -/** Offset 0x1C2D - Race To Halt +/** Offset 0x1C35 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. 0: Disable; 1: Enable @@ -2874,66 +2874,59 @@ **/ UINT8 RaceToHalt; -/** Offset 0x1C2E - Reserved +/** Offset 0x1C36 - Reserved **/ - UINT8 Reserved62; + UINT8 Reserved63; -/** Offset 0x1C2F - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x1C37 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x1C30 - Reserved +/** Offset 0x1C38 - Reserved **/ - UINT8 Reserved63[4]; + UINT8 Reserved64[4]; -/** Offset 0x1C34 - Intel Turbo Boost Max Technology 3.0 - Enable/Disable Intel(R) Turbo Boost Max Technology 3.0 support. Disabling will report - the maximum ratio of the slowest core in _CPC object. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x1C35 - Enable or Disable C1 Cstate Demotion +/** Offset 0x1C3C - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x1C36 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x1C3D - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate Un-Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x1C37 - Minimum Ring ratio limit override +/** Offset 0x1C3E - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x1C38 - Maximum Ring ratio limit override +/** Offset 0x1C3F - Maximum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x1C39 - Enable or Disable Per Core P State OS control +/** Offset 0x1C40 - Enable or Disable Per Core P State OS control Enable/Disable Per Core P state OS control mode. When set, the highest core request is used for all other core requests. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnablePerCorePState; -/** Offset 0x1C3A - Enable or Disable HwP Autonomous Per Core P State OS control +/** Offset 0x1C41 - Enable or Disable HwP Autonomous Per Core P State OS control Disable Autonomous PCPS Autonomous will request the same value for all cores all the time. 0: Disable; 1: Enable $EN_DIS **/ UINT8 EnableHwpAutoPerCorePstate; -/** Offset 0x1C3B - Enable or Disable HwP Autonomous EPP Grouping +/** Offset 0x1C42 - Enable or Disable HwP Autonomous EPP Grouping Enable EPP grouping Autonomous will request the same values for all cores with same EPP. Disable EPP grouping autonomous will not necessarily request same values for all cores with same EPP. 0: Disable ; 1: Enable @@ -2941,7 +2934,7 @@ **/ UINT8 EnableHwpAutoEppGrouping; -/** Offset 0x1C3C - Enable Configurable TDP +/** Offset 0x1C43 - Enable Configurable TDP Applies cTDP(Assured Power) initialization settings based on non-cTDP(Assured Power) or cTDP(Assured Power). Default is 1: Applies to cTDP(Assured Power); if 0 then applies non-cTDP(Assured Power) and BIOS will bypass cTDP(Assured Power) initialzation flow @@ -2949,42 +2942,42 @@ **/ UINT8 ApplyConfigTdp; -/** Offset 0x1C3D - Reserved +/** Offset 0x1C44 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved65; -/** Offset 0x1C3E - Dual Tau Boost +/** Offset 0x1C45 - Dual Tau Boost Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W sku. When DPTF is enabled this feature is ignored. 0: Disable; 1: Enable $EN_DIS **/ UINT8 DualTauBoost; -/** Offset 0x1C3F - Reserved +/** Offset 0x1C46 - Reserved **/ - UINT8 Reserved65[33]; + UINT8 Reserved66[34]; -/** Offset 0x1C60 - End of Post message +/** Offset 0x1C68 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x1C61 - D0I3 Setting for HECI Disable +/** Offset 0x1C69 - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x1C62 - Mctp Broadcast Cycle +/** Offset 0x1C6A - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x1C63 - ME Unconfig on RTC clear +/** Offset 0x1C6B - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2992,159 +2985,159 @@ **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x1C64 - Enforce Enhanced Debug Mode +/** Offset 0x1C6C - Enforce Enhanced Debug Mode Determine if ME should enter Enhanced Debug Mode. 0: disable, 1: enable $EN_DIS **/ UINT8 EnforceEDebugMode; -/** Offset 0x1C65 - Reserved +/** Offset 0x1C6D - Reserved **/ - UINT8 Reserved66[17]; + UINT8 Reserved67[17]; -/** Offset 0x1C76 - Enable LOCKDOWN SMI +/** Offset 0x1C7E - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x1C77 - Enable LOCKDOWN BIOS Interface +/** Offset 0x1C7F - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x1C78 - Unlock all GPIO pads +/** Offset 0x1C80 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x1C79 - PCH Unlock SideBand access +/** Offset 0x1C81 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x1C7A - Reserved +/** Offset 0x1C82 - Reserved **/ - UINT8 Reserved67[2]; + UINT8 Reserved68[2]; -/** Offset 0x1C7C - PCIE RP Ltr Max Snoop Latency +/** Offset 0x1C84 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[29]; -/** Offset 0x1CB6 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x1CBE - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[29]; -/** Offset 0x1CF0 - PCIE RP Snoop Latency Override Mode +/** Offset 0x1CF8 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[29]; -/** Offset 0x1D0D - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x1D15 - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[29]; -/** Offset 0x1D2A - PCIE RP Snoop Latency Override Value +/** Offset 0x1D32 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[29]; -/** Offset 0x1D64 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x1D6C - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[29]; -/** Offset 0x1D81 - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x1D89 - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[29]; -/** Offset 0x1D9E - PCIE RP Non Snoop Latency Override Value +/** Offset 0x1DA6 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[29]; -/** Offset 0x1DD8 - PCIE RP Slot Power Limit Scale +/** Offset 0x1DE0 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[29]; -/** Offset 0x1DF5 - Reserved +/** Offset 0x1DFD - Reserved **/ - UINT8 Reserved68; + UINT8 Reserved69; -/** Offset 0x1DF6 - PCIE RP Slot Power Limit Value +/** Offset 0x1DFE - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[29]; -/** Offset 0x1E30 - PCIE RP Enable Port8xh Decode +/** Offset 0x1E38 - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x1E31 - PCIE Port8xh Decode Port Index +/** Offset 0x1E39 - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x1E32 - PCH Energy Reporting +/** Offset 0x1E3A - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x1E33 - PCH Sata Test Mode +/** Offset 0x1E3B - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x1E34 - PCH USB OverCurrent mapping lock enable +/** Offset 0x1E3C - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x1E35 - Low Power Mode Enable/Disable config mask +/** Offset 0x1E3D - Low Power Mode Enable/Disable config mask Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4. **/ UINT8 PmcLpmS0ixSubStateEnableMask; -/** Offset 0x1E36 - Reserved +/** Offset 0x1E3E - Reserved **/ - UINT8 Reserved69[5]; + UINT8 Reserved70[5]; -/** Offset 0x1E3B - PMC C10 dynamic threshold dajustment enable +/** Offset 0x1E43 - PMC C10 dynamic threshold dajustment enable Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs $EN_DIS **/ UINT8 PmcC10DynamicThresholdAdjustment; -/** Offset 0x1E3C - Reserved +/** Offset 0x1E44 - Reserved **/ - UINT8 Reserved70[36]; + UINT8 Reserved71[36]; -/** Offset 0x1E60 - FspEventHandler +/** Offset 0x1E68 - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. **/ UINT32 FspEventHandler; -/** Offset 0x1E64 - Reserved +/** Offset 0x1E6C - Reserved **/ - UINT8 Reserved71[28]; + UINT8 Reserved72[28]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -3163,11 +3156,11 @@ **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x1E80 +/** Offset 0x1E88 **/ UINT8 Rsvd600[6]; -/** Offset 0x1E86 +/** Offset 0x1E8E **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/74803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Gerrit-Change-Number: 74803 Gerrit-PatchSet: 1 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: treewide: Add missing include guards to chip.h
by Jan Samek (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tim Crawford, Jeremy Soller, Christian Walter, Mario Scheithauer, Arthur Heymans, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74749 ) Change subject: treewide: Add missing include guards to chip.h ...................................................................... Patch Set 4: (1 comment) File src/drivers/i2c/rtd2132/chip.h: https://review.coreboot.org/c/coreboot/+/74749/comment/ec0e7708_7a2355eb PS3, Line 3: RTD_2132 > maybe without underscore Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3 Gerrit-Change-Number: 74749 Gerrit-PatchSet: 4 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 09:07:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: treewide: Add missing include guards to chip.h
by Jan Samek (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tim Crawford, Jeremy Soller, Christian Walter, Arthur Heymans, Werner Zeh, Jan Samek. Hello Tim Crawford, Jeremy Soller, Christian Walter, Mario Scheithauer, Arthur Heymans, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74749 to look at the new patch set (#4). Change subject: treewide: Add missing include guards to chip.h ...................................................................... treewide: Add missing include guards to chip.h Some of the chip.h files in the tree are missing the include guards. This patch adds them in order to avoid potential redefinions of symbols contained in these headers, when they are included multiple times in static.c generated by sconfig. Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/cpu/intel/haswell/chip.h M src/cpu/intel/model_2065x/chip.h M src/cpu/intel/model_206ax/chip.h M src/drivers/generic/alc1015/chip.h M src/drivers/generic/bayhub/chip.h M src/drivers/generic/bayhub_lv2/chip.h M src/drivers/generic/max98357a/chip.h M src/drivers/generic/nau8315/chip.h M src/drivers/i2c/cs35l53/chip.h M src/drivers/i2c/cs42l42/chip.h M src/drivers/i2c/da7219/chip.h M src/drivers/i2c/max98373/chip.h M src/drivers/i2c/max98390/chip.h M src/drivers/i2c/max98396/chip.h M src/drivers/i2c/max98927/chip.h M src/drivers/i2c/nau8825/chip.h M src/drivers/i2c/pca9538/chip.h M src/drivers/i2c/pcf8523/chip.h M src/drivers/i2c/ptn3460/chip.h M src/drivers/i2c/rt1011/chip.h M src/drivers/i2c/rt5663/chip.h M src/drivers/i2c/rtd2132/chip.h M src/drivers/i2c/rx6110sa/chip.h M src/drivers/i2c/tas5825m/chip.h M src/drivers/i2c/tpm/chip.h M src/drivers/intel/ish/chip.h M src/drivers/net/phy/m88e1512/chip.h 27 files changed, 151 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/74749/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I550a514e72a8dd4db602e7ceffccd81aa36446e3 Gerrit-Change-Number: 74749 Gerrit-PatchSet: 4 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/rex/variants/screebo: Generate RAM IDs
by Subrata Banik (Code Review) 27 Apr '23

27 Apr '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Kun Liu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74802 ) Change subject: mb/google/rex/variants/screebo: Generate RAM IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Gerrit-Change-Number: 74802 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 27 Apr 2023 09:03:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2023