coreboot-gerrit March 2023

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[M] Change in coreboot[master]: soc/intel/xeon_sp/uncore.c: Add CXL memory into memory map
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Attention is currently required from: Jonathan Zhang, TimLiu-SMCI, Johnny Lin, David Hendricks, Christian Walter, Angel Pons, Shuming Chu (Shuming), Arthur Heymans. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72617 ) Change subject: soc/intel/xeon_sp/uncore.c: Add CXL memory into memory map ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/72617/comment/918125e8_6329c8b0 PS7, Line 241: #if CONFIG(SOC_INTEL_HAS_CXL) Can this not be a regular if instead of preprocessor #if? -- To view, visit https://review.coreboot.org/c/coreboot/+/72617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f Gerrit-Change-Number: 72617 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 05 Mar 2023 16:08:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: intelblocks/vtd: Add VT-d block with DMA protection API
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Attention is currently required from: Michał Żygowski, Angel Pons. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68449 ) Change subject: intelblocks/vtd: Add VT-d block with DMA protection API ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/vtd/vtd.c: https://review.coreboot.org/c/coreboot/+/68449/comment/464a4393_cd5eb971 PS9, Line 297: #if ENV_RAMSTAGE && CONFIG(ENABLE_EARLY_DMA_PROTECTION) Nit: Could this be moved around just the boot_state_init entry or does that cause a compile issue? If it can, it'd be good to let the compiler check the function, then the linker would optimize it out if it's not used. -- To view, visit https://review.coreboot.org/c/coreboot/+/68449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Gerrit-Change-Number: 68449 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Elias Souza <eliascontato(a)protonmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Mar 2023 16:00:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/geralt: Add NAU8318 support for Geralt
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73413 ) Change subject: mb/google/geralt: Add NAU8318 support for Geralt ...................................................................... mb/google/geralt: Add NAU8318 support for Geralt Add a config "USE_NAU8318" to enable NAU8318 support. NAU8318 is another speaker used in Geralt. NAU8318 supports beep function via GPIO control. So we configure the GPIO pins and pass them to the payload. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443 Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73413 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/geralt/Kconfig M src/mainboard/google/geralt/chromeos.c M src/mainboard/google/geralt/gpio.h 3 files changed, 37 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index af4d7e0..e8e365d 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -68,6 +68,9 @@ config USE_MAX98390 bool "MAX98390" +config USE_NAU8318 + bool "NAU8318" + endchoice endif diff --git a/src/mainboard/google/geralt/chromeos.c b/src/mainboard/google/geralt/chromeos.c index 10fc9d3..ab9f1d6 100644 --- a/src/mainboard/google/geralt/chromeos.c +++ b/src/mainboard/google/geralt/chromeos.c @@ -20,6 +20,7 @@ gpio_output(GPIO_EN_SPKR, 0); gpio_output(GPIO_RST_SPKR_L, 0); gpio_output(GPIO_XHCI_INIT_DONE, 0); + gpio_output(GPIO_BEEP_ON_OD, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -27,7 +28,6 @@ struct lb_gpio chromeos_gpios[] = { {GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt"}, - {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"}, {GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); @@ -46,6 +46,12 @@ {GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "speaker reset"}, }; lb_add_gpios(gpios, max98390_gpios, ARRAY_SIZE(max98390_gpios)); + } else if (CONFIG(USE_NAU8318)) { + struct lb_gpio nau8318_gpios[] = { + {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"}, + {GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"}, + }; + lb_add_gpios(gpios, nau8318_gpios, ARRAY_SIZE(nau8318_gpios)); } } diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h index 126cfe8..c05b804 100644 --- a/src/mainboard/google/geralt/gpio.h +++ b/src/mainboard/google/geralt/gpio.h @@ -8,9 +8,9 @@ #define GPIO_AP_DISP_BKLTEN GPIO(GPIO01) #define GPIO_AP_EC_WARM_RST_REQ GPIO(DPI_HSYNC) #define GPIO_AP_WP_ODL GPIO(GPIO15) -#define GPIO_BEEP_ON_OD GPIO(I2SIN_WS) +#define GPIO_BEEP_ON_OD GPIO(KPROW0) #define GPIO_EC_AP_INT_ODL GPIO(DPI_DE) -#define GPIO_EN_SPKR GPIO(I2SIN_D2) +#define GPIO_EN_SPKR GPIO(I2SIN_D1) #define GPIO_GSC_AP_INT_ODL GPIO(GPIO00) #define GPIO_RST_SPKR_L GPIO(I2SO2_D1) #define GPIO_XHCI_INIT_DONE GPIO(DPI_CK) -- To view, visit https://review.coreboot.org/c/coreboot/+/73413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443 Gerrit-Change-Number: 73413 Gerrit-PatchSet: 6 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/geralt: Add MAX98390 support for Geralt
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73412 ) Change subject: mb/google/geralt: Add MAX98390 support for Geralt ...................................................................... mb/google/geralt: Add MAX98390 support for Geralt Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/geralt/Kconfig M src/mainboard/google/geralt/chromeos.c M src/mainboard/google/geralt/gpio.h M src/mainboard/google/geralt/mainboard.c M src/soc/mediatek/mt8188/include/soc/addressmap.h 5 files changed, 80 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index 8de4fea..af4d7e0 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -60,4 +60,14 @@ config SDCARD_INIT bool default y + +choice + prompt "Speaker AMP for Geralt" + default USE_MAX98390 if BOARD_GOOGLE_GERALT + +config USE_MAX98390 + bool "MAX98390" + +endchoice + endif diff --git a/src/mainboard/google/geralt/chromeos.c b/src/mainboard/google/geralt/chromeos.c index 266fc78..10fc9d3 100644 --- a/src/mainboard/google/geralt/chromeos.c +++ b/src/mainboard/google/geralt/chromeos.c @@ -18,6 +18,7 @@ /* Set up GPOs */ gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_EN_SPKR, 0); + gpio_output(GPIO_RST_SPKR_L, 0); gpio_output(GPIO_XHCI_INIT_DONE, 0); } @@ -39,6 +40,13 @@ }; lb_add_gpios(gpios, sd_card_gpios, ARRAY_SIZE(sd_card_gpios)); } + + if (CONFIG(USE_MAX98390)) { + struct lb_gpio max98390_gpios[] = { + {GPIO_RST_SPKR_L.id, ACTIVE_LOW, -1, "speaker reset"}, + }; + lb_add_gpios(gpios, max98390_gpios, ARRAY_SIZE(max98390_gpios)); + } } int tis_plat_irq_status(void) diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h index 36f488e..126cfe8 100644 --- a/src/mainboard/google/geralt/gpio.h +++ b/src/mainboard/google/geralt/gpio.h @@ -12,8 +12,13 @@ #define GPIO_EC_AP_INT_ODL GPIO(DPI_DE) #define GPIO_EN_SPKR GPIO(I2SIN_D2) #define GPIO_GSC_AP_INT_ODL GPIO(GPIO00) +#define GPIO_RST_SPKR_L GPIO(I2SO2_D1) #define GPIO_XHCI_INIT_DONE GPIO(DPI_CK) +#define GPIO_I2SI1_LRCK GPIO(I2SO2_D2) +#define GPIO_I2SI1_BCK GPIO(I2SIN_D3) +#define GPIO_I2SO1_D0 GPIO(GPIO11) + #define GPIO_EDP_BL_PWM_1V8 GPIO(DISP_PWM1) #define GPIO_EDP_HPD_1V8 GPIO(GPIO17) #define GPIO_EN_PP3300_EDP_DISP_X GPIO(DSI1_LCM_RST) diff --git a/src/mainboard/google/geralt/mainboard.c b/src/mainboard/google/geralt/mainboard.c index ee8b005..1422398 100644 --- a/src/mainboard/google/geralt/mainboard.c +++ b/src/mainboard/google/geralt/mainboard.c @@ -3,13 +3,42 @@ #include <bootmode.h> #include <device/device.h> #include <soc/bl31.h> +#include <soc/i2c.h> #include <soc/msdc.h> #include <soc/mt6359p.h> +#include <soc/mtcmos.h> #include <soc/usb.h> #include "display.h" #include "gpio.h" +#define AFE_SE_SECURE_CON (AUDIO_BASE + 0x17a8) + +static void configure_i2s(void) +{ + /* Audio PWR */ + mtcmos_audio_power_on(); + mtcmos_protect_audio_bus(); + + /* Switch to normal mode */ + write32p(AFE_SE_SECURE_CON, 0x0); + + /* SoC I2S */ + gpio_set_mode(GPIO_I2SI1_LRCK, PAD_I2SO2_D2_FUNC_TDMIN_LRCK); + gpio_set_mode(GPIO_I2SI1_BCK, PAD_I2SIN_D3_FUNC_TDMIN_BCK); + gpio_set_mode(GPIO_I2SO1_D0, PAD_GPIO11_FUNC_I2SO1_D0); +} + +static void configure_audio(void) +{ + if (CONFIG(USE_MAX98390)) { + printk(BIOS_DEBUG, "Configure MAX98390 audio\n"); + + mtk_i2c_bus_init(I2C0, I2C_SPEED_FAST); + configure_i2s(); + } +} + static void mainboard_init(struct device *dev) { mt6359p_init_pmif_arb(); @@ -23,6 +52,8 @@ mtk_msdc_configure_emmc(true); + configure_audio(); + if (CONFIG(SDCARD_INIT)) mtk_msdc_configure_sdcard(); diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index a5a3c00..63f0596 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -57,6 +57,7 @@ DPM_PM_SRAM_BASE2 = IO_PHYS + 0x00A00000, DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000, DPM_CFG_BASE2 = IO_PHYS + 0x00A40000, + AUDIO_BASE = IO_PHYS + 0x00B10000, UART0_BASE = IO_PHYS + 0x01001100, UART1_BASE = IO_PHYS + 0x01001200, UART2_BASE = IO_PHYS + 0x01001300, -- To view, visit https://review.coreboot.org/c/coreboot/+/73412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Gerrit-Change-Number: 73412 Gerrit-PatchSet: 6 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/geralt: Add mtcmos bus protection for display
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73411 ) Change subject: mb/google/geralt: Add mtcmos bus protection for display ...................................................................... mb/google/geralt: Add mtcmos bus protection for display Enable bus protection for display to avoid bus hang and incomplete bus transaction. BUG=b:264204465 TEST=test firmware and kernel display pass for MIPI panel on geralt. Change-Id: Iac61a69f2b84966dd468442daaa59d83eec775aa Signed-off-by: Liju-Clr Chen <liju-clr.chen(a)mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73411 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/geralt/display.c 1 file changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c index 396d6e0..bbdd808 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/mainboard/google/geralt/display.c @@ -27,6 +27,7 @@ printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); mtcmos_display_power_on(); + mtcmos_protect_display_bus(); panel->configure_panel_backlight(); panel->power_on(); -- To view, visit https://review.coreboot.org/c/coreboot/+/73411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac61a69f2b84966dd468442daaa59d83eec775aa Gerrit-Change-Number: 73411 Gerrit-PatchSet: 5 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/hades: Add baseboard device tree
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73415 ) Change subject: mb/google/hades: Add baseboard device tree ...................................................................... mb/google/hades: Add baseboard device tree Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb 1 file changed, 139 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ivy Jian: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index a5e2217..c05658a 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -1,4 +1,124 @@ chip soc/intel/alderlake + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_E" + register "pmc_gpe0_dw2" = "GPP_F" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # S0ix enable + register "s0ix_enable" = "1" + + # DPTF enable + register "dptf_enable" = "1" + + register "tcc_offset" = "10" # TCC of 90 + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_EMPTY" + register "usb3_ports[2]" = "USB3_PORT_EMPTY" + register "usb3_ports[3]" = "USB3_PORT_EMPTY" + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" + + register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_50_MS" + register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_1S" + register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S" + register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS" + register "pch_reset_power_cycle_duration" = "POWER_CYCLE_DURATION_1S" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # FIVR RFI Spread Spectrum 1.5% + register "fivr_spread_spectrum" = "FIVR_SS_1_5" + + # Disable C state auto-demotion for all brya baseboards + register "disable_c1_state_auto_demotion" = "1" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end + device ref dtt on end + device ref tcss_xhci on end + device ref xhci on end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref heci1 on end + device ref sata on end + device ref uart0 on end + device ref gspi1 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref hda on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/73415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Gerrit-Change-Number: 73415 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Add bus protection for audio/video mtcmos
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73375 ) Change subject: soc/mediatek/mt8188: Add bus protection for audio/video mtcmos ...................................................................... soc/mediatek/mt8188: Add bus protection for audio/video mtcmos Bus protection is a HW mechanism to avoid bus hang and incomplete bus transactions. Bus protection HW must be enabled while the receiver of the transaction is not able to respond. BUG=b:264204465 TEST=build pass Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Signed-off-by: garmin chang <garmin.chang(a)mediatek.corp-partner.google.com> Signed-off-by: jason-ch chen <jason-ch.chen(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73375 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/mtcmos.c 1 file changed, 94 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/mtcmos.c b/src/soc/mediatek/mt8188/mtcmos.c index 3143b01..2339f37 100644 --- a/src/soc/mediatek/mt8188/mtcmos.c +++ b/src/soc/mediatek/mt8188/mtcmos.c @@ -5,7 +5,78 @@ #include <soc/mtcmos.h> #include <soc/spm.h> +enum { + VPPSYS0_PROT_STEP_6_MASK = 0x00100000, + VPPSYS0_PROT_STEP_5_MASK = 0x00276C16, + VPPSYS0_PROT_STEP_4_MASK = 0x00800000, + VPPSYS0_PROT_STEP_3_MASK = 0x00800200, + VPPSYS0_PROT_STEP_2_MASK = 0x80302846, + VPPSYS0_PROT_STEP_1_MASK = 0x00000400, + VDOSYS0_PROT_STEP_4_MASK = 0x00000060, + VDOSYS0_PROT_STEP_3_MASK = 0x00800000, + VDOSYS0_PROT_STEP_2_MASK = 0x00000020, + VDOSYS0_PROT_STEP_1_MASK = 0x00100000, + VPPSYS1_PROT_STEP_3_MASK = 0x00040000, + VPPSYS1_PROT_STEP_2_MASK = 0x00800000, + VPPSYS1_PROT_STEP_1_MASK = 0x00000020, + VDOSYS1_PROT_STEP_3_MASK = 0x00000400, + VDOSYS1_PROT_STEP_2_MASK = 0x00400000, + VDOSYS1_PROT_STEP_1_MASK = 0x40000000, + ADSP_PROT_STEP_2_MASK = 0x00001000, + ADSP_PROT_STEP_1_MASK = 0x00100000, + AUDIO_PROT_STEP_2_MASK = 0x00600000, + AUDIO_PROT_STEP_1_MASK = 0x00000F00, +}; + void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd) { clrbits32(&mtk_spm->ext_buck_iso, pd->ext_buck_iso_bits); } + +void mtcmos_protect_display_bus(void) +{ + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VPPSYS0_PROT_STEP_6_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_5_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_4_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS0_PROT_STEP_3_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS0_PROT_STEP_2_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr, + VPPSYS0_PROT_STEP_1_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_sub_infra_vdnr_clr, + VDOSYS0_PROT_STEP_4_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_3_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr, + VDOSYS0_PROT_STEP_2_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS0_PROT_STEP_1_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VPPSYS1_PROT_STEP_3_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_2_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VPPSYS1_PROT_STEP_1_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr_2, + VDOSYS1_PROT_STEP_3_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_2_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_mm_clr, + VDOSYS1_PROT_STEP_1_MASK); +} + +void mtcmos_protect_audio_bus(void) +{ + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2, + ADSP_PROT_STEP_2_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2, + ADSP_PROT_STEP_1_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP_2_MASK); + write32(&mt8188_infracfg_ao->infra_topaxi_protecten_clr_2, + AUDIO_PROT_STEP_1_MASK); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/73375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14aa63c4934073a14552cef64f40657d0197bbe1 Gerrit-Change-Number: 73375 Gerrit-PatchSet: 4 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: DEMO:CEZANNE: Add --use-combo
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Attention is currently required from: Bao Zheng. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73326 ) Change subject: DEMO:CEZANNE: Add --use-combo ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I don't understand the subject of the commit message. Is this supposed to be merged? I'm going to hold off on merging the following patches since they're based on top of this one. -- To view, visit https://review.coreboot.org/c/coreboot/+/73326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I106344f4100934095a6f5b4e7fd9c4f0c0c3874a Gerrit-Change-Number: 73326 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Comment-Date: Sun, 05 Mar 2023 15:43:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/xhci: Add struct for capability registers
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Attention is currently required from: Robert Zieba, Raul Rangel, Karthik Ramasubramanian. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69915 ) Change subject: device/xhci: Add struct for capability registers ...................................................................... Patch Set 13: (1 comment) File src/include/device/xhci.h: https://review.coreboot.org/c/coreboot/+/69915/comment/00b1a4f6_7fd10888 PS11, Line 109: > Does it need to be packed to reflect the exact register structure? Marking it as packed shouldn't change anything here. The two uint8s and the uint16 will cleanly go into 32 bits, so there shouldn't be any padding. Are you seeing something I don't see? -- To view, visit https://review.coreboot.org/c/coreboot/+/69915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Gerrit-Change-Number: 69915 Gerrit-PatchSet: 13 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sun, 05 Mar 2023 15:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

[L] Change in coreboot[master]: device/xhci: Add functions to work with resource pointers
by Martin L Roth (Code Review) 05 Mar '23

05 Mar '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Add functions to work with resource pointers ...................................................................... device/xhci: Add functions to work with resource pointers The XHCI device functions currently use functions that require a access to the device tree. Create variant of these functions that can operate with a resource* as an argument and refactor the existing device*-based functions to operate by calling the resource*-based variants. This is useful for stages like SMM that may not have access to the device tree. BRANCH=guybrush BUG=b:186792595 TEST=Ran on skyrim device, verified that XHCI ACPI tables are still generated correctly. Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69914 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/device/Makefile.inc M src/device/xhci.c A src/device/xhci_resource.c M src/include/device/xhci.h 4 files changed, 165 insertions(+), 95 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 3018ef9..7da6ea8 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -61,7 +61,8 @@ ramstage-y += resource_allocator_common.c ramstage-y += resource_allocator_v4.c -ramstage-$(CONFIG_XHCI_UTILS) += xhci.c +ramstage-$(CONFIG_XHCI_UTILS) += xhci.c xhci_resource.c +smm-$(CONFIG_XHCI_UTILS) += xhci_resource.c ramstage-y += gpio.c ramstage-y += mdio.c diff --git a/src/device/xhci.c b/src/device/xhci.c index f7c5958..0961d0c 100644 --- a/src/device/xhci.c +++ b/src/device/xhci.c @@ -2,31 +2,18 @@ #include <console/console.h> #include <device/mmio.h> +#include <device/device.h> #include <device/pci_def.h> #include <device/xhci.h> -#include <string.h> - -union xhci_ext_caps_header { - uint32_t val; - struct { - uint32_t cap_id : 8; - uint32_t next_ptr : 8; - uint32_t reserved : 16; - }; -}; enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, void (*callback)(void *context, const struct xhci_ext_cap *cap)) { - struct resource *res; - uint32_t *ext_cap_ptr; - uint32_t ext_caps_word_offset; - union xhci_ext_caps_header header; - struct xhci_ext_cap cap; + const struct resource *res; - if (!device || !callback) - return CB_ERR_ARG; + if (!device) + return CB_ERR; res = probe_resource(device, PCI_BASE_ADDRESS_0); if (!res) { @@ -35,89 +22,24 @@ return CB_ERR; } - if (!(res->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "%s: BAR is not assigned\n", __func__); - return CB_ERR; - } - - if (res->limit > 0xFFFFFFFF) { - printk(BIOS_ERR, "%s: 64-bit BAR is not supported\n", __func__); - return CB_ERR; - } - - ext_caps_word_offset = read16(res2mmio(res, XHCI_HCCPARAMS1_XECP, 0)); - - if (!ext_caps_word_offset) { - printk(BIOS_ERR, "%s: No extended capabilities defined\n", __func__); - return CB_ERR; - } - - ext_cap_ptr = res2mmio(res, ext_caps_word_offset << 2, 0); - - while ((uintptr_t)ext_cap_ptr < (uintptr_t)res->limit) { - header.val = read32(ext_cap_ptr); - - cap.cap_id = header.cap_id; - - if (header.cap_id == XHCI_ECP_CAP_ID_SUPP) { - cap.supported_protocol.reg0 = header.val; - cap.supported_protocol.reg1 = read32(ext_cap_ptr + 1); - cap.supported_protocol.reg2 = read32(ext_cap_ptr + 2); - } - - callback(context, &cap); - - if (!header.next_ptr) - break; - - ext_cap_ptr += header.next_ptr; - } - - return CB_SUCCESS; -} - -struct supported_usb_cap_context { - void *context; - void (*callback)(void *context, const struct xhci_supported_protocol *data); -}; - -static void xhci_supported_usb_cap_handler(void *context, const struct xhci_ext_cap *cap) -{ - const struct xhci_supported_protocol *data; - struct supported_usb_cap_context *internal_context = context; - - if (cap->cap_id != XHCI_ECP_CAP_ID_SUPP) - return; - - data = &cap->supported_protocol; - - if (memcmp(data->name, "USB ", 4)) { - printk(BIOS_DEBUG, "%s: Unknown Protocol: %.*s\n", __func__, - (int)sizeof(data->name), data->name); - return; - } - - internal_context->callback(internal_context->context, data); + return xhci_resource_for_each_ext_cap(res, context, callback); } enum cb_err xhci_for_each_supported_usb_cap( const struct device *device, void *context, void (*callback)(void *context, const struct xhci_supported_protocol *data)) { - struct supported_usb_cap_context internal_context = { - .context = context, - .callback = callback, - }; + const struct resource *res; - return xhci_for_each_ext_cap(device, &internal_context, xhci_supported_usb_cap_handler); -} + if (!device) + return CB_ERR; -void xhci_print_supported_protocol(const struct xhci_supported_protocol *supported_protocol) -{ - printk(BIOS_DEBUG, "xHCI Supported Protocol:\n"); - printk(BIOS_DEBUG, " Major: %#x, Minor: %#x, Protocol: '%.*s'\n", - supported_protocol->major_rev, supported_protocol->minor_rev, - (int)sizeof(supported_protocol->name), supported_protocol->name); - printk(BIOS_DEBUG, " Port Offset: %d, Port Count: %d\n", - supported_protocol->port_offset, supported_protocol->port_count); + res = probe_resource(device, PCI_BASE_ADDRESS_0); + if (!res) { + printk(BIOS_ERR, "%s: Unable to find BAR resource for %s\n", __func__, + dev_path(device)); + return CB_ERR; + } + + return xhci_resource_for_each_supported_usb_cap(res, context, callback); } diff --git a/src/device/xhci_resource.c b/src/device/xhci_resource.c new file mode 100644 index 0000000..31f2610 --- /dev/null +++ b/src/device/xhci_resource.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/mmio.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <device/xhci.h> +#include <string.h> + +union xhci_ext_caps_header { + uint32_t val; + struct { + uint32_t cap_id : 8; + uint32_t next_ptr : 8; + uint32_t reserved : 16; + }; +}; + +enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, + void (*callback)(void *context, + const struct xhci_ext_cap *cap)) +{ + uint32_t *ext_cap_ptr; + uint32_t ext_caps_word_offset; + union xhci_ext_caps_header header; + struct xhci_ext_cap cap; + + if (!res || !callback) + return CB_ERR_ARG; + + if (!(res->flags & IORESOURCE_ASSIGNED)) { + printk(BIOS_ERR, "%s: BAR is not assigned\n", __func__); + return CB_ERR; + } + + if (res->limit > 0xFFFFFFFF) { + printk(BIOS_ERR, "%s: 64-bit BAR is not supported\n", __func__); + return CB_ERR; + } + + ext_caps_word_offset = read16(res2mmio(res, XHCI_HCCPARAMS1_XECP, 0)); + + if (!ext_caps_word_offset) { + printk(BIOS_ERR, "%s: No extended capabilities defined\n", __func__); + return CB_ERR; + } + + ext_cap_ptr = res2mmio(res, ext_caps_word_offset << 2, 0); + + while ((uintptr_t)ext_cap_ptr < (uintptr_t)res->limit) { + header.val = read32(ext_cap_ptr); + + cap.cap_id = header.cap_id; + + if (header.cap_id == XHCI_ECP_CAP_ID_SUPP) { + cap.supported_protocol.reg0 = header.val; + cap.supported_protocol.reg1 = read32(ext_cap_ptr + 1); + cap.supported_protocol.reg2 = read32(ext_cap_ptr + 2); + } + + callback(context, &cap); + + if (!header.next_ptr) + break; + + ext_cap_ptr += header.next_ptr; + } + + return CB_SUCCESS; +} + +struct supported_usb_cap_context { + void *context; + void (*callback)(void *context, const struct xhci_supported_protocol *data); +}; + +static void xhci_supported_usb_cap_handler(void *context, const struct xhci_ext_cap *cap) +{ + const struct xhci_supported_protocol *data; + struct supported_usb_cap_context *internal_context = context; + + if (cap->cap_id != XHCI_ECP_CAP_ID_SUPP) + return; + + data = &cap->supported_protocol; + + if (memcmp(data->name, "USB ", 4)) { + printk(BIOS_DEBUG, "%s: Unknown Protocol: %.*s\n", __func__, + (int)sizeof(data->name), data->name); + return; + } + + internal_context->callback(internal_context->context, data); +} + +enum cb_err xhci_resource_for_each_supported_usb_cap( + const struct resource *res, void *context, + void (*callback)(void *context, const struct xhci_supported_protocol *data)) +{ + struct supported_usb_cap_context internal_context = { + .context = context, + .callback = callback, + }; + + return xhci_resource_for_each_ext_cap(res, &internal_context, + xhci_supported_usb_cap_handler); +} + +void xhci_print_supported_protocol(const struct xhci_supported_protocol *supported_protocol) +{ + printk(BIOS_DEBUG, "xHCI Supported Protocol:\n"); + printk(BIOS_DEBUG, " Major: %#x, Minor: %#x, Protocol: '%.*s'\n", + supported_protocol->major_rev, supported_protocol->minor_rev, + (int)sizeof(supported_protocol->name), supported_protocol->name); + printk(BIOS_DEBUG, " Port Offset: %d, Port Count: %d\n", + supported_protocol->port_offset, supported_protocol->port_count); +} diff --git a/src/include/device/xhci.h b/src/include/device/xhci.h index b9c784e..861bf22 100644 --- a/src/include/device/xhci.h +++ b/src/include/device/xhci.h @@ -97,6 +97,9 @@ /** * Iterates over the xHCI Extended Capabilities List. */ +enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, + void (*callback)(void *context, + const struct xhci_ext_cap *cap)); enum cb_err xhci_for_each_ext_cap(const struct device *device, void *context, void (*callback)(void *context, const struct xhci_ext_cap *cap)); @@ -108,6 +111,9 @@ enum cb_err xhci_for_each_supported_usb_cap( const struct device *device, void *context, void (*callback)(void *context, const struct xhci_supported_protocol *data)); +enum cb_err xhci_resource_for_each_supported_usb_cap( + const struct resource *res, void *context, + void (*callback)(void *context, const struct xhci_supported_protocol *data)); void xhci_print_supported_protocol(const struct xhci_supported_protocol *supported_protocol); -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 14 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2023