coreboot-gerrit March 2023

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[S] Change in coreboot[master]: spd/lp5: Add new memory part to LP5 list
by build bot (Jenkins) (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Frank Wu, Dtrain Hsu, Subrata Banik, Eric Lai, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73489 ) Change subject: spd/lp5: Add new memory part to LP5 list ...................................................................... Patch Set 3: Verified+1 (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171483): https://review.coreboot.org/c/coreboot/+/73489/comment/1a41e1ce_bff9e8e4 PS3, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/73489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a Gerrit-Change-Number: 73489 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 10:19:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Update RAM ID table
by John Su (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Frank Wu, Dtrain Hsu, Jason Nien, Eric Lai, Martin Roth. Hello Frank Wu, build bot (Jenkins), Dtrain Hsu, Jason Nien, Eric Lai, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73510 to look at the new patch set (#2). Change subject: mb/google/skyrim/var/markarth: Update RAM ID table ...................................................................... mb/google/skyrim/var/markarth: Update RAM ID table Add new ram_id:0011 for micron MT62F1G32D2DS-023 WT:B. Add new ram_id:0100 for micron MT62F2G32D4DS-023 WT:B. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) MT62F1G32D2DS-023 WT:B 3 (0011) H58G66BK8BX067 4 (0100) MT62F2G32D4DS-023 WT:B 4 (0100) BUG=b:271188237 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/skyrim/variants/markarth/memory/Makefile.inc M src/mainboard/google/skyrim/variants/markarth/memory/dram_id.generated.txt M src/mainboard/google/skyrim/variants/markarth/memory/mem_parts_used.txt 3 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/73510/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba Gerrit-Change-Number: 73510 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: spd/lp5: Add new memory part to LP5 list
by John Su (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Frank Wu, Dtrain Hsu, Subrata Banik, Eric Lai, Karthik Ramasubramanian. Hello Frank Wu, build bot (Jenkins), Dtrain Hsu, Subrata Banik, Eric Lai, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73489 to look at the new patch set (#3). Change subject: spd/lp5: Add new memory part to LP5 list ...................................................................... spd/lp5: Add new memory part to LP5 list Add MICRON memory part MT62F1G32D2DS-023 and MT62F2G32D4DS-023 to LP5 global list. Attributes are derived from data sheets. Also, regenerate the SPD files for SoC using the newly added parts. BUG=b:271188237 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M spd/lp5/memory_parts.json M spd/lp5/set-0/parts_spd_manifest.generated.txt M spd/lp5/set-1/parts_spd_manifest.generated.txt 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/73489/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6675a68b7a515bd6d21db3ea2da762b06dee017a Gerrit-Change-Number: 73489 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: payloads/edk2: Add an option to use EDK2 Universal Payload
by Lean Sheng Tan (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Sean Rhodes, Martin L Roth, Patrick Rudolph, Matt DeVillier, Stefan Reinauer. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/65934 ) Change subject: payloads/edk2: Add an option to use EDK2 Universal Payload ...................................................................... Patch Set 46: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/65934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17cc86d5eac0d5d91551ba5bea73fbc07ebdf0d3 Gerrit-Change-Number: 65934 Gerrit-PatchSet: 46 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Mar 2023 10:08:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: Documentation/sbom: Add SBOM Documentation
by Lean Sheng Tan (Code Review) 06 Mar '23

06 Mar '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68995 ) Change subject: Documentation/sbom: Add SBOM Documentation ...................................................................... Documentation/sbom: Add SBOM Documentation Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68995 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M Documentation/index.md A Documentation/sbom/sbom.md A Documentation/sbom/sbom_generation.plantuml A Documentation/sbom/sbom_generation.svg 4 files changed, 310 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/Documentation/index.md b/Documentation/index.md index 45ad837..44e52a2 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -193,6 +193,7 @@ * [SuperIO](superio/index.md) * [Vendorcode](vendorcode/index.md) * [Utilities](util.md) +* [Software Bill of Materials](sbom/sbom.md) * [Project infrastructure & services](infrastructure/index.md) * [Boards supported in each release directory](releases/boards_supported_on_branches.md) * [Release notes](releases/index.md) diff --git a/Documentation/sbom/sbom.md b/Documentation/sbom/sbom.md new file mode 100644 index 0000000..c4984f9 --- /dev/null +++ b/Documentation/sbom/sbom.md @@ -0,0 +1,156 @@ +# Software Bill of Materials (SBOM) + +SBOM is a collection of information of each software component +you are supplying/building. Similar to a package manager on Linux +based systems, it holds information of as many software parts as +possible. This information can be a version, name of the software, URL, +license information and more. A SBOM can be saved in various formats. +In coreboot it's saved as "uSWID" file. uSWID is not a standard or +specification but it doesn't need to be, since it's basically just an +array/list of CoSWID (Concise Software Identification) files which in +turn are specified by a RFC specification. CoSWID files are saved in a +CBOR format. CBOR is like JSON if JSON were a binary format. Similar +to a package manager the CoSWID format can link multiple softwares +together. For example on most modern Intel systems FSP is included as +a dependency of coreboot. That kind of relationship between software +components (among others) can be expressed in an uSWID file. That makes +firmware/software much more transparent. One could for example create a +software that takes a coreboot firmware image as input and +automatically creates a graph with all software components the coreboot +image contains and their relationship to each other. + + +## SWID/CoSWID + +SWID is a standard hidden behind an ISO paywall. +It generally identifies/describes Software components. Since SWID files +are written in XML, they can get too large for devices with network and +storage constraints. CoSWID is basically SWID but in CBOR binary +format, which makes it far smaller compared to its big brother. Also, +CoSWID is a RFC specification (so publicly accessible). Therefore +CoSWID is the standard used in coreboot SBOM. But one CoSWID file/tag +can only describe one single software, but since software is usually +composed of multiple parts (especially in firmware with many binary +blobs) uSWID was born as a container format to hold multiple CoSWID +files. It also has a magic value, that makes software capable of +extracting uSWID/CoSWID data without the need to understand the +underlying format of the binary (in coreboot it's the CBFS and in EDK2 +it's the COFF). To get a simple overview of how a SWID/CoSWID file +looks like, just take a look at the various "templates" in src/sbom/. +There are of course other SBOM specifications out there, but most of +them are rather blown up and don't support a binary format at all. + + +## coreboot implementation + +Quick overview of how things are generated: + +![Generation of an SBOM File in coreboot][sbom_generation] + +[sbom_generation]: sbom_generation.svg + +After all SBOM data has been fetched from all the software components, +the 'goswid' tool links them all together into one sbom.uswid file. +Therefore the goswid tool is basically a linker that takes multiple +CoSWID/SWID files and converts them into one uSWID file. Although the +image shows only Files in JSON format it is also possible to supply +them in XML or CBOR format. + +The final SBOM file is located inside the CBFS. +For each software component in coreboot SBOM, there is an option in +Kconfig (usually called `CONFIG_INCLUDE_[software-name]_SBOM`) to either +include or not include SBOM metadata for the specified software. +Furthermore there is a `CONFIG_SBOM_[software-name]_PATH` option which +contains a path to a SWID/CoSWID file in a format of choice +(being either JSON, XML or CBOR). `CONFIG_SBOM_[software-name]_PATH` +option usually defaults to a very generic CoSWID file in JSON format +(which are stored in src/sbom/). That at least gives minimal +information like the name of the software and maybe a version. +But it is always preferred, that the `CONFIG_SBOM_[software-name]_PATH` +is set to a custom CoSWID/SWID file that contains much more information +(like version/commit-hash, license, URL, dependencies, ...). +Therefore using the defaults is by any means to be avoided, since they +hold very little information or even worse wrong information. +Furthermore some of these Kconfig options have a suboption +(usually called `CONFIG_SBOM_[software-name]_GENERATE`) to generate +some basic SBOM data for the specified software component, in order to +get at least some bit of information about it by analyzing the binary +(for binary blobs) or querying information via git (for open source +projects). This is for example currently done for all payloads. For +each payload the commit hash used in the build is taken and put into +the SBOM file. For open-source projects (like all payloads) crucial +information like the current commit-hash of the payload can easily be +put into the SBOM file. Extracting information out of binary blobs is a +bit trickier for obvious reasons. For closed source binary blobs it is +therefore recommended that vendors and software-engineers create a SBOM +file as part of their build process and add a path to that SBOM file +via Kconfig options in coreboot (`CONFIG_SBOM_[software-name]_PATH`). +That way the final SBOM has much more useful and correct data. + + +## Build coreboot with SBOM + +Directly under the 'General setup' Kconfig menu is a +'Software Bill of Materials (SBOM)' submenu where all options are to +enable/disable SBOM integration in to the corebeoot build. +Therefore one can just enable/disable them via `make menuconfig`. + + +## What to do as Developer of a binary blob (which is used in coreboot) + +1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format +as part of your software build process + +2. Supply that generated File along with your binary blob (preferably +not inside the blob) + +3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your +defconfig pointing to your [software-name] generated File. + + +## What to do as Developer of an open source project (which is used in coreboot) + +1. Generate a SWID/CoSWID/uSWID file in either JSON, XML or CBOR format +as part of your software's build process. For example in form of a +Makefile target. + +2. Change src/sbom/Makefile.inc (in order to know where to find the +CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which +builds said software. For example for GRUB2 that could mean to add a +Makefile target in payloads/external/GRUB2/Makefile. + + +## Problems + +What to do if the binary blob that is included in coreboot's build +already has a SBOM file embedded in the binary? One could supply the +path of the software binary itself (e.g. me.bin) as SBOM file path for +the software in question. Which would basically mean to set +`CONFIG_SBOM_[software-name]_PATH=/path/to/me.bin`. This is possible +since the 'goswid' tooling is able to extract uSWID information out of +an unknown binary format because of uSWIDs magic value. But even if +coreboot can extract the uSWID data there is still the question of what +to do next. One can do one of the following: + + - Do not include the Software's SBOM data in the final SBOM of + coreboot. Data would not be duplicated, but therefore not included + in coreboot SBOM file. + + - Extract the uSWID/CoSWID information from the binary and also + include it in the coreboot SBOM. That would mean, that SBOM data + is duplicated. + +The first solution should in general be preferred, since its no +problem if SBOM data is located at multiple locations/binaries if they +don't have a direct dependency on each other. It would be good if +software that cannot run on its own only supplies the SBOM data along +with it as kind of extra file instead of embedded in an unknown binary +blob. coreboot can then just take it and include it in its own SBOM +file. If on the other hand the binary can function on its own (e.g. EC +or BMC binary), it is generally preferred that the software supplies +its own SBOM data and coreboot just simply doesn't include it in its +own SBOM file. That would make a more or less clear distinction and +avoids duplication in case the BMC or EC is updated (without updating +coreboot). The distinction is not always easy and this problem is +currently not considered in the implementation, since none of the +software components currently create a SBOM file on their own. diff --git a/Documentation/sbom/sbom_generation.plantuml b/Documentation/sbom/sbom_generation.plantuml new file mode 100644 index 0000000..e8d9f1e --- /dev/null +++ b/Documentation/sbom/sbom_generation.plantuml @@ -0,0 +1,61 @@ +@startuml + +map "src/sbom/compiler-gcc.json" as gcc { + software-name => GCC + version => x.y.z + ... => ... +} +map "src/sbom/intel-me.json" as me { + software-name => Intel Mangement Engine + ... => ... +} +map "src/sbom/intel-microcode.json" as ucode { + software-name => Intel Microcode + ... => ... +} +map "src/sbom/generic-ec.json" as ec { + software-name => ecxyz + ... => ... +} +map "src/sbom/generic-fsp.json" as fsp { + software-name => Firmware Support Package + version => x.y.z + ... => ... +} +map "src/sbom/payload-[...].json" as payload { + software-name => ... + version => x.y.z + ... => ... +} +map "src/sbom/coreboot.json" as coreboot { + software-name => coreboot + version => x.y.z + url => coreboot.rocks + ... => ... +} +object "sbom.uswid" as uswid { + merged SBOM data in binary format +} +object goswid { + # ./goswid + --compiler gcc.json + --parent coreboot.json + --requires fsp.json,payload.json + intel-me.json + intel-ec.json + intel-ucode.json + --output sbom.uswid +} + +left to right direction +gcc --> goswid +me --> goswid +ucode --> goswid +goswid <-- ec +goswid <-- fsp +goswid <-- payload + +coreboot -up> goswid +goswid -up> uswid + +@enduml diff --git a/Documentation/sbom/sbom_generation.svg b/Documentation/sbom/sbom_generation.svg new file mode 100644 index 0000000..2a5e4f5 --- /dev/null +++ b/Documentation/sbom/sbom_generation.svg @@ -0,0 +1,79 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentStyleType="text/css" height="401px" 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https://review.coreboot.org/c/coreboot/+/68995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39fbcba60a0fbdbed9f662119ed7692c0a0fd30e Gerrit-Change-Number: 68995 Gerrit-PatchSet: 13 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Richard Hughes <richard(a)hughsie.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81
by build bot (Jenkins) (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Subrata Banik, Ronak Kanabar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73374 ) Change subject: vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81 ...................................................................... Patch Set 4: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171481): https://review.coreboot.org/c/coreboot/+/73374/comment/395d7700_cb645779 PS4, Line 14: SocTraceHubMemReg1Size. 'depricated' may be misspelled - perhaps 'deprecated'? -- To view, visit https://review.coreboot.org/c/coreboot/+/73374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Gerrit-Change-Number: 73374 Gerrit-PatchSet: 4 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 09:32:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81
by Kilari Raasi (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Subrata Banik, Ronak Kanabar. Hello build bot (Jenkins), Subrata Banik, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73374 to look at the new patch set (#4). Change subject: vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81 ...................................................................... vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81 Update header files for FSP for Meteor Lake platform to version 3064_81, previous version being 2523_80.. FSPM: 1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size SocTraceHubMemReg1Size. 2. Remove depricated UPD RDODTT. 3. Address offset changes. FSPS: 1. Address offset changes. FspUpd.h: 1.Corrected UPD signatures. BUG=b:TBD Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 3 files changed, 1,039 insertions(+), 978 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/73374/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/73374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Gerrit-Change-Number: 73374 Gerrit-PatchSet: 4 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[master]: mb/google/geralt: Set +-5.7V to TPS65132s EEPROM
by Yidi Lin (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: cong yang. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73443 ) Change subject: mb/google/geralt: Set +-5.7V to TPS65132s EEPROM ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29236818444cac84d42386a371cd8934048ff948 Gerrit-Change-Number: 73443 Gerrit-PatchSet: 5 Gerrit-Owner: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 09:21:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Configure Acoustic noise mitigation
by Frank Chu (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73491 ) Change subject: mb/google/brya/var/marasov: Configure Acoustic noise mitigation ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Gerrit-Change-Number: 73491 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 09:16:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Configure Acoustic noise mitigation
by Frank Chu (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73491 to look at the new patch set (#2). Change subject: mb/google/brya/var/marasov: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/marasov: Configure Acoustic noise mitigation - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:271788117 TEST=build FW and system power on. Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/73491/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Gerrit-Change-Number: 73491 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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