coreboot-gerrit March 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Print `mrc_cache` size in decimal
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Dinesh Gehlot, Ivy Jian, Andrey Petrov. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73490 ) Change subject: drivers/intel/fsp2_0: Print `mrc_cache` size in decimal ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: any different for %zu? -- To view, visit https://review.coreboot.org/c/coreboot/+/73490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69feeb36423e47a5992c9f27d9a7042803a492cd Gerrit-Change-Number: 73490 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Mar 2023 00:32:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Uday M Bhat. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72881 ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/72881/comment/ea2d9a8d_5571223c PS6, Line 322: /* GPP_S00 : [] ==> SDW_HP_CLK */ : PAD_NC(GPP_S00, NONE), : /* GPP_S01 : [] ==> SDW_HP_DATA */ : PAD_NC(GPP_S01, NONE), > Can this be implemented in similar lines as this […] yes, please use FW config as used to do. -- To view, visit https://review.coreboot.org/c/coreboot/+/72881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday M Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Uday M Bhat <uday.m.bhat(a)intel.com> Gerrit-Comment-Date: Tue, 07 Mar 2023 00:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Uday M Bhat <uday.m.bhat(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Rename touchscreen signals as per latest Rex schematics
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli, Eran Mitrani, Martin L Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71795 ) Change subject: mb/google/rex: Rename touchscreen signals as per latest Rex schematics ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Gerrit-Change-Number: 71795 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Mar 2023 00:27:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: Enable Fast VMode for taeko
by Nick Vaccaro (Code Review) 06 Mar '23

06 Mar '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73373 ) Change subject: mb/google/brya/var/taeko: Enable Fast VMode for taeko ...................................................................... mb/google/brya/var/taeko: Enable Fast VMode for taeko Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73373 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index e13da23..00d7e69 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -44,6 +44,10 @@ end end chip soc/intel/alderlake + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .enable_fast_vmode = 1, + }" + # As per Intel Advisory doc#723158, the change is required to prevent possible # display flickering issue. register "usb2_phy_sus_pg_disable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/73373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c Gerrit-Change-Number: 73373 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: use RPL FSP headers
by Nick Vaccaro (Code Review) 06 Mar '23

06 Mar '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73371 ) Change subject: mb/google/brya/var/taeko: use RPL FSP headers ...................................................................... mb/google/brya/var/taeko: use RPL FSP headers To support an RPL SKU on taeko, taeko must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for taeko so that it will use the RPL FSP headers for taeko. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot taeko to kernel. Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Cq-Depend: chrome-internal:5544049, chromium:4302529 Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73371 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 27 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index f63efdf..67e8f38 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -169,6 +169,7 @@ select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX if DRIVERS_GENESYSLOGIC_GL9763E select CHROMEOS_WIFI_SAR if CHROMEOS + select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_TAEKO4ES bool "-> Taeko4ES" -- To view, visit https://review.coreboot.org/c/coreboot/+/73371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1 Gerrit-Change-Number: 73371 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPU
by Nick Vaccaro (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Daisuke Nojiri, Tarun Tuli. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 11 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 23:12:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Extend sd_hold for touchpad/touchscreen
by Reka Norman (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Tyler Wang, Nick Vaccaro. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73349 ) Change subject: mb/google/nissa/var/craask: Extend sd_hold for touchpad/touchscreen ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2f72da80ffe8d4dd494caabbe1a97e52a81e78 Gerrit-Change-Number: 73349 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quantatw.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quantatw.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quantatw.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 23:07:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Allow port descriptors to be overridden
by Karthik Ramasubramanian (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth, Jason Nien, Arthur Heymans, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73294 ) Change subject: mb/google/skyrim: Allow port descriptors to be overridden ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/73294/comment/2fc703a0_142a0d78 PS2, Line 97: if (!*dxio_num || !*dxio_descs) : { : *dxio_descs = skyrim_mdn_dxio_descriptors; : *dxio_num = ARRAY_SIZE(skyrim_mdn_dxio_descriptors); : } > Sure, we can do that. […] Looking through the use-case it sounds Kconfig makes sense to me too. If the concerned config is not enabled, then use the baseboard port_descriptors.c. Else use the override port_descriptors.c from the variant. -- To view, visit https://review.coreboot.org/c/coreboot/+/73294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Gerrit-Change-Number: 73294 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 23:04:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/asrock/b75m-itx: Make NIC a child device below the right PCIe port
by Kevin Keijzer (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Kevin Keijzer. Hello Kevin Keijzer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/73516 to review the following change. Change subject: mb/asrock/b75m-itx: Make NIC a child device below the right PCIe port ...................................................................... mb/asrock/b75m-itx: Make NIC a child device below the right PCIe port The Realtek RTL8111E NIC is currently not defined as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as is appropriate for on-board ethernet devices. Additionally, the comment in devicetree.cb stating that PCIe port 6 is the ethernet controller is incorrect. It's actually port 4. This patch moves the comment to the right port, and defines the NIC as a child device of said port, so that it's properly defined as an on-board device. Change-Id: Ie1e3a757a6bd6c7dd1702ced177d13711978dcc4 Signed-off-by: Kevin Keijzer <kevin(a)quietlife.nl> --- M src/mainboard/asrock/b75m-itx/devicetree.cb 1 file changed, 27 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/73516/1 diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 9fdad95..5b3387a 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -50,11 +50,13 @@ end device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on # PCIe Port #4 - subsystemid 0x1849 0x1e16 + device pci 1c.3 on # PCIe Port #4, Realtek PCIe GbE Controller + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1849 0x1e16 + end end device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on # PCIe Port #6, Realtek PCIe GbE Controller + device pci 1c.5 on # PCIe Port #6 subsystemid 0x1849 0x1e1a end device pci 1c.6 off end # PCIe Port #7 -- To view, visit https://review.coreboot.org/c/coreboot/+/73516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1e3a757a6bd6c7dd1702ced177d13711978dcc4 Gerrit-Change-Number: 73516 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Keijzer Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/stoneyridge/romstage: pass C state control IO base address
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73497 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge/romstage: pass C state control IO base address ...................................................................... soc/amd/stoneyridge/romstage: pass C state control IO base address Instead of hoping that the default the C state control IO address in binaryPI won't interfere with any other IO space usage in coreboot, assign the ACPI_CSTATE_CONTROL value to the CStateIoBaseAddress platform config structure element to make sure that binaryPI will use a known address for the IO port based C state control. binaryPI will write this address to the MSR_CSTATE_ADDRESS and will then also use these IO ports in the _CST packages in the PSTATE SSDT, so changing this won't cause a mismatch between those two. The default CStateIoBaseAddress in the FT4 Stoneyridge binaryPI used on Careena is 0x1770, so this didn't collide with any other IO space registers, but it's still much better to tell binaryPI which exact IO addresses to use. TEST=On Careena MSR_CSTATE_ADDRESS now contains the ACPI_CSTATE_CONTROL IO base address 0x420 and the PSTATE SSDT has the IO address 0x421 in the _CST package entry for the second C state which are both the expected values. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/romstage.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/73497/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 Gerrit-Change-Number: 73497 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2023