coreboot-gerrit March 2023

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[M] Change in coreboot[master]: soc/amd/cezanne/acpi: rework C state info table handling
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73500 ) Change subject: soc/amd/cezanne/acpi: rework C state info table handling ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id97fcb74ff3d48994a3181d9c31cbbeb5a76c60a Gerrit-Change-Number: 73500 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:53:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/picasso/acpi: rework C state info table handling
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73499 ) Change subject: soc/amd/picasso/acpi: rework C state info table handling ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6bd8879ce5968b24893b43041be98db55a4c3c6 Gerrit-Change-Number: 73499 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Add Intel Trace Hub driver
by Pratikkumar V Prajapati (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Nico Huber, Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72722 ) Change subject: soc/intel/common: Add Intel Trace Hub driver ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > That's a good question. IMO, Not all devices may have 4+ GiB RAM. […] Nico, Sorry for the long pause in replying. Is the platform has more than 4GB of memory it can be used to store larger amount of traces from Intel Trace HUB (TH) IP. If the memory is smaller than 4GB, we can still user internal buffer of TH to store traces. In either cases we can still use streaming to the host machine to get traces. This driver adds support for devices that have larger memory. If the platform has memory larger than 4GB then FSP will allocate region for traces in DRAM (per UPD params), if platform has lesser memory then we need to use internal buffer or use streaming mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/72722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Gerrit-Change-Number: 72722 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:53:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73428 ) Change subject: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/acpi/cpu_power_state.c: https://review.coreboot.org/c/coreboot/+/73428/comment/d51fc1b5_47258b5f PS4, Line 49: uint32_t cstate_io_base_address = If put cstate_io_base_address in write_cstate_entry as static. Maybe you don't need pass every time? -- To view, visit https://review.coreboot.org/c/coreboot/+/73428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Gerrit-Change-Number: 73428 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:51:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/common/block/acpi/cpu_power_state: use definition for bit_offset
by Eric Lai (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73498 ) Change subject: soc/amd/common/block/acpi/cpu_power_state: use definition for bit_offset ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9edc681efab15b5ceba91c8105f7dc6d687d8be8 Gerrit-Change-Number: 73498 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:46:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Add Intel Trace Hub driver
by Pratikkumar V Prajapati (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Sridhar Siricilla. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72722 ) Change subject: soc/intel/common: Add Intel Trace Hub driver ...................................................................... Patch Set 4: (1 comment) This change is ready for review. Patchset: PS3: > > FSP allocates memory for tracehub to save traces (depending on UPD params). […] Sorry for the long pause in replying. >>Seems like in this driver code, you are unconditionally checking the HOB, what if the HOB is not present ? does that mean we don't need to provide the fixed BAR as TH might not have configured/initialized? I am not sure what condition you are expecting! If the HOB is not present, we simply do not mark any region reserved. I am calling pci_dev_read_resources from tracehub_read_resources. pci_dev_read_resources would set the BAR, isnt it? Did i miss anything? >>But from that, you first need to make sure that ITH is bus/device/function enabled by boot firmware aka coreboot. I dont think its needed as this driver will get called only when coreboot enumerated PCIe IDs are matched with pci_device_ids mentioned in my driver. This match will not happen if TH is disabled from device tree. >>First and for most, you need to make sure that TH is not disabled by boot firmware, then assign the UPDs (SOCTracehobmode, AetTraceHubmode and/or PchTraceHubMode) are updated. Without those IMO, the Hob will not be produced and the added driver code is just not in use. Since this is stand-alone PCIe driver, and I have mentioned TH PCI IDs in pci_device_ids for this driver, no need to check if the boot firmware has TH disabled. This diver will not get called if the TH is disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/72722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Gerrit-Change-Number: 72722 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:44:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper
by build bot (Jenkins) (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73428 ) Change subject: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/block/acpi/cpu_power_state.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-171520): https://review.coreboot.org/c/coreboot/+/73428/comment/d0b43b8a_67d0abee PS4, Line 60: for (i = 0; i < cstate_count; i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/73428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Gerrit-Change-Number: 73428 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Mar 2023 02:14:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/73428 to look at the new patch set (#4). Change subject: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper ...................................................................... soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper Introduce the get_cstate_info helper function that populates the caller- provided cstate_values array with the data returned by the SoC-specific get_cstate_config_data function. From the array get_cstate_config_data returns, only the ctype, latency and power fields are used, so the rest can be left uninitialized. Those 3 fields are compile-time constants. For each entry, write_cstate_entry will generate the corresponding resource information from the given data. In the C1 case where ctype is 1, the state is entered via a MWAIT instruction, while the higher C states are entered by doing an IO read from a specific IO address. This IO address is x - 1 bytes into the IO region starting at MSR_CSTATE_ADDRESS for the Cx state. So for example C2 is entered by reading from the C state IO base address + 1. This resource information is generated during runtime, since the contents of MSR_CSTATE_ADDRESS aren't necessarily known at compile-time. MAX_CSTATE_COUNT is introduced so that the caller can allocate and pass a buffer with space for the maximum number of C state entries. This maximum number corresponds to the number of IO addresses the CPU traps beginning from MSR_CSTATE_ADDRESS. In practice, it's unlikely that more than 3 or maybe 4 C states will be available though. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d --- M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/cpu_power_state.c M src/soc/amd/common/block/include/amdblocks/cpu.h 4 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/73428/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/73428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Gerrit-Change-Number: 73428 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73506 ) Change subject: soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h ...................................................................... soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.h The bit position of the P state enable bit in the 8 P state MSRs is identical for all AMD chips including the family 15h model 60h APU that lives outside of soc/amd. The other bits in those 8 MSRs are more or less family- and model-specific. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77 --- M src/include/cpu/amd/msr.h M src/soc/amd/cezanne/include/soc/msr.h M src/soc/amd/common/block/acpi/cpu_power_state.c M src/soc/amd/glinda/include/soc/msr.h M src/soc/amd/mendocino/include/soc/msr.h M src/soc/amd/phoenix/include/soc/msr.h M src/soc/amd/picasso/include/soc/msr.h 7 files changed, 18 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/73506/1 diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 1fd7ec7..1c1a825 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -41,6 +41,9 @@ #define PS_STS_REG 0xC0010063 #define PSTATE_0_MSR 0xC0010064 #define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate)) +#define PSTATE_DEF_HI_ENABLE_SHIFT 31 +#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) + #define MSR_PATCH_LOADER 0xC0010020 #define MSR_COFVID_STS 0xC0010071 diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 83357c1..5a0bac1 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -4,8 +4,6 @@ #define AMD_CEZANNE_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c index 614a715..03f42d7 100644 --- a/src/soc/amd/common/block/acpi/cpu_power_state.c +++ b/src/soc/amd/common/block/acpi/cpu_power_state.c @@ -7,7 +7,6 @@ #include <console/console.h> #include <cpu/amd/msr.h> #include <cpu/x86/msr.h> -#include <soc/msr.h> #include <types.h> /* diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index 5500ab5..51ab585 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -6,8 +6,6 @@ #define AMD_GLINDA_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index 4b25195..0fe4b6f 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -4,8 +4,6 @@ #define AMD_MENDOCINO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 57001ad..30ac560 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -6,8 +6,6 @@ #define AMD_PHOENIX_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index ca6b25a..2392614 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -8,8 +8,6 @@ #define AMD_PICASSO_MSR_H /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ -#define PSTATE_DEF_HI_ENABLE_SHIFT 31 -#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT) #define PSTATE_DEF_LO_CUR_DIV_SHIFT 30 #define PSTATE_DEF_LO_CUR_DIV_MASK (0x3 << PSTATE_DEF_LO_CUR_DIV_SHIFT) #define PSTATE_DEF_LO_CUR_VAL_SHIFT 22 -- To view, visit https://review.coreboot.org/c/coreboot/+/73506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77 Gerrit-Change-Number: 73506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73428 ) Change subject: soc/amd/common/block/acpi/cpu_power_state: add get_cstate_info helper ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/73428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d Gerrit-Change-Number: 73428 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Mar 2023 01:44:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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