coreboot-gerrit March 2023

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[M] Change in coreboot[master]: [Test_Me]: Add intel CPUID F6x support
by Elyes Haouas (Code Review) 06 Mar '23

06 Mar '23

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68782 to look at the new patch set (#3). Change subject: [Test_Me]: Add intel CPUID F6x support ...................................................................... [Test_Me]: Add intel CPUID F6x support Change-Id: Iaacb856a0064ea57cdcec11a76fab1cd340e2ed8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/intel/Kconfig A src/cpu/intel/model_f6x/Kconfig A src/cpu/intel/model_f6x/Makefile.inc A src/cpu/intel/model_f6x/model_f6x_init.c M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/speedstep/speedstep.c 7 files changed, 121 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/68782/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/68782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaacb856a0064ea57cdcec11a76fab1cd340e2ed8 Gerrit-Change-Number: 68782 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/common/pi/agesawrapper: pass C state control IO base address
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73497 ) Change subject: soc/amd/common/pi/agesawrapper: pass C state control IO base address ...................................................................... soc/amd/common/pi/agesawrapper: pass C state control IO base address Instead of hoping that the default the C state control IO address in binaryPI won't interfere with any other IO space usage in coreboot, assign the ACPI_CSTATE_CONTROL value to the CStateIoBaseAddress platform config structure element to make sure that binaryPI will use a known address for the IO port based C state control. binaryPI will write this address to the MSR_CSTATE_ADDRESS and will then also use these IO ports in the _CST packages in the PSTATE SSDT, so changing this won't cause a mismatch between those two. The default CStateIoBaseAddress in the FT4 Stoneyridge binaryPI used on Careena is 0x1770, so this didn't collide with any other IO space registers, but it's still much better to tell binaryPI which exact IO addresses to use. TEST=On Careena MSR_CSTATE_ADDRESS now contains the ACPI_CSTATE_CONTROL IO base address 0x420 and the PSTATE SSDT has the IO address 0x421 in the _CST package entry for the second C state which are both the expected values. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 --- M src/soc/amd/common/pi/agesawrapper.c M src/soc/amd/stoneyridge/include/soc/iomap.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/73497/1 diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index 2539a1d..ae6ee78 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -7,6 +7,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> #include <amdblocks/ioapic.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/northbridge.h> #include <soc/cpu.h> @@ -114,6 +115,10 @@ soc_customize_init_early(EarlyParams); OemCustomizeInitEarly(EarlyParams); + /* Make binaryPi use ACPI_CSTATE_CONTROL as C state control IO range. It gets written + into MSR_CSTATE_ADDRESS and used in the _CST packages in the PSTATE SSDT. */ + EarlyParams->PlatformConfig.CStateIoBaseAddress = ACPI_CSTATE_CONTROL; + timestamp_add_now(TS_AGESA_INIT_EARLY_START); status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_END); diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 31cd12b..0977bb3 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -30,6 +30,7 @@ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define SMB_BASE_ADDR 0xb00 #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 Gerrit-Change-Number: 73497 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: lint/checkpatch: Silent braces warning for single statement
by Elyes Haouas (Code Review) 06 Mar '23

06 Mar '23

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/72628 ) Change subject: lint/checkpatch: Silent braces warning for single statement ...................................................................... Abandoned see 73515 -- To view, visit https://review.coreboot.org/c/coreboot/+/72628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib31fbda63a59cf856313cb5965019eff5eebf2c0 Gerrit-Change-Number: 72628 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: util/lint: Ignore braces around single line statements
by Elyes Haouas (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73515 ) Change subject: util/lint: Ignore braces around single line statements ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488 Gerrit-Change-Number: 73515 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 21:37:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/lint: Ignore braces around single line statements
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73515 ) Change subject: util/lint: Ignore braces around single line statements ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488 Gerrit-Change-Number: 73515 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 21:28:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/lint: Ignore braces around single line statements
by Martin L Roth (Code Review) 06 Mar '23

06 Mar '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73515 ) Change subject: util/lint: Ignore braces around single line statements ...................................................................... util/lint: Ignore braces around single line statements In a recent coreboot leadership meeting, the decision was made to allow (but not require) braces around single line statements if the author wishes to put them in. This patch removes the checks for single line statement blocks, while still checking for other issues in braces. Just because they're allowed now, please do not reformat the entire codebase to add them. coreboot has a policy of not making widespread changes to the entire codebase unless something actually violates the style guidelines. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488 --- M util/lint/checkpatch.pl 1 file changed, 33 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/73515/1 diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index a8a91e8..c2efdbc 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -5631,8 +5631,9 @@ $sum_allowed += $_; } if ($sum_allowed == 0) { - WARN("BRACES", - "braces {} are not necessary for any arm of this statement\n" . $herectx); + # coreboot has decided to allow braces around single line statement blocks + #WARN("BRACES", + # "braces {} are not necessary for any arm of this statement\n" . $herectx); } elsif ($sum_allowed != $allow && $seen != $allow) { CHK("BRACES", @@ -5683,13 +5684,14 @@ $allowed = 1; } } - if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { - my $cnt = statement_rawlines($block); - my $herectx = get_stat_here($linenr, $cnt, $here); - - WARN("BRACES", - "braces {} are not necessary for single statement blocks\n" . $herectx); - } + # coreboot has decided to allow braces around single line statement blocks + #if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { + # my $cnt = statement_rawlines($block); + # my $herectx = get_stat_here($linenr, $cnt, $here); + # + # WARN("BRACES", + # "braces {} are not necessary for single statement blocks\n" . $herectx); + #} } # check for single line unbalanced braces -- To view, visit https://review.coreboot.org/c/coreboot/+/73515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I137b10889ec880959c4c1b035dc54bf8ebf32488 Gerrit-Change-Number: 73515 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPU
by Caveh Jalali (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Daisuke Nojiri, Tarun Tuli, Nick Vaccaro. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73217 ) Change subject: mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPU ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/73217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Gerrit-Change-Number: 73217 Gerrit-PatchSet: 11 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Daisuke Nojiri <dnojiri(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 21:08:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: drop link_hotplug from port descriptors
by Martin Roth (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Nien, Martin Roth. Martin Roth has uploaded a new patch set (#2) to the change originally created by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/73512 ) Change subject: mb/google/skyrim: drop link_hotplug from port descriptors ...................................................................... mb/google/skyrim: drop link_hotplug from port descriptors These ports are not hot pluggable, so drop the parameter, which will result it in being set to zero / not enabled. BUG=none TEST=build boot skyrim, verify all PCIe devices functional. BRANCH=skyrim Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/73512/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Gerrit-Change-Number: 73512 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/skyrim: override winterhold & whiterun PCIe config
by Martin Roth (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth, Jason Nien, Martin Roth. Martin Roth has uploaded a new patch set (#3) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/73441 ) Change subject: mb/google/skyrim: override winterhold & whiterun PCIe config ...................................................................... mb/google/skyrim: override winterhold & whiterun PCIe config Winterhold & Whiterun boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d --- M src/mainboard/google/skyrim/variants/whiterun/Makefile.inc A src/mainboard/google/skyrim/variants/whiterun/port_descriptors.c M src/mainboard/google/skyrim/variants/winterhold/Makefile.inc A src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c 4 files changed, 257 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/73441/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Gerrit-Change-Number: 73441 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/skyrim: Allow port descriptors to be overridden
by Martin Roth (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth, Jason Nien, Matt DeVillier, Arthur Heymans, Karthik Ramasubramanian. Martin Roth has uploaded a new patch set (#3) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/73294 ) Change subject: mb/google/skyrim: Allow port descriptors to be overridden ...................................................................... mb/google/skyrim: Allow port descriptors to be overridden This allows variants to override the skyrim port descriptors. BUG=None TEST=Tested with following patches BRANCH=skyrim Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 --- M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 2 files changed, 49 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/73294/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/73294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Gerrit-Change-Number: 73294 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2023