coreboot-gerrit March 2023

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[S] Change in coreboot[master]: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73427 ) Change subject: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs ...................................................................... soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs The legacy ACPI CPU control registers in IO space where the first 4 IO locations control the CPU throttling value don't exist any more on the Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS in set_cstate_io_addr which will cause accesses from the 8 IO addresses beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads from those IO addresses will cause the CPU to enter low C states. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/include/soc/iomap.h M src/soc/amd/picasso/include/soc/iomap.h 6 files changed, 27 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index fc04b25..e4fe00f 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -42,7 +42,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 8fd3715..8151b96 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -24,6 +24,6 @@ msr_t cst_addr; cst_addr.hi = 0; - cst_addr.lo = ACPI_CPU_CONTROL; + cst_addr.lo = ACPI_CSTATE_CONTROL; wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index bb8588c..b335b3f 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -50,7 +50,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index 630940bb..1e1120c 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 5a1488b..b12b48c 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -48,7 +48,7 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index c70c64e..26022ef 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -69,8 +69,8 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ -/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */ +#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ +/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CSTATE_CONTROL on are trapped in CPU core */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Gerrit-Change-Number: 73427 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/picasso/include/iomap: add comment about ACPI IO assignment
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73423 ) Change subject: soc/amd/picasso/include/iomap: add comment about ACPI IO assignment ...................................................................... soc/amd/picasso/include/iomap: add comment about ACPI IO assignment Finally figured out why ACPI_GPE0_BLK only being 4 bytes after ACPI_CPU_CONTROL won't work and its due to the CPU trapping 8 IO addresses from ACPI_CPU_CONTROL on for C state control. This is set up in set_cstate_io_addr by writing the ACPI_CPU_CONTROL value into MSR_CSTATE_ADDRESS. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73423 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 646844c..c70c64e 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -69,8 +69,8 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) -/* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ +/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */ -- To view, visit https://review.coreboot.org/c/coreboot/+/73423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131 Gerrit-Change-Number: 73423 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73422 ) Change subject: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define ...................................................................... soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define Picasso and newer don't implement the P_CNT register to control the CPU duty cycle and also trap the C state control IO addresses directly in the CPU, so those won't reach the FCH. This register is unused in the Picasso code and not even defined any more in the Cezanne PPR. The Picasso PPR does define this register, but since it's useless and might even just be a leftover form a pre-Zen CPU generation, drop the define. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73422 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index a3fb1a2..31f3ed6 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -47,7 +47,6 @@ #define TIMER_STS BIT(0) #define PM1_CNT_BLK 0x62 #define PM_TMR_BLK 0x64 -#define PM_CPU_CTRL 0x66 #define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_CONF 0x74 -- To view, visit https://review.coreboot.org/c/coreboot/+/73422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Gerrit-Change-Number: 73422 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs
by Fred Reitberger (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73427 ) Change subject: soc/amd: rename ACPI_CPU_CONTROL to ACPI_CSTATE_CONTROL for non-CAR CPUs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b Gerrit-Change-Number: 73427 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Mar 2023 17:19:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/include/iomap: add comment about ACPI IO assignment
by Fred Reitberger (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73423 ) Change subject: soc/amd/picasso/include/iomap: add comment about ACPI IO assignment ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131 Gerrit-Change-Number: 73423 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Mar 2023 17:19:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define
by Fred Reitberger (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73422 ) Change subject: soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Gerrit-Change-Number: 73422 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Mar 2023 17:18:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: use RPL FSP headers
by Nick Vaccaro (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli, Joey Peng, Nick Vaccaro, Bob Moragues. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73371 ) Change subject: mb/google/brya/var/taeko: use RPL FSP headers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1 Gerrit-Change-Number: 73371 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Mar 2023 17:14:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/taeko: Enable Fast VMode for taeko
by Nick Vaccaro (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tarun Tuli, Joey Peng, Nick Vaccaro, Bob Moragues. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73373 ) Change subject: mb/google/brya/var/taeko: Enable Fast VMode for taeko ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c Gerrit-Change-Number: 73373 Gerrit-PatchSet: 3 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Mon, 06 Mar 2023 17:14:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: drop link_hotplug from port descriptors
by Matt DeVillier (Code Review) 06 Mar '23

06 Mar '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73512 ) Change subject: mb/google/skyrim: drop link_hotplug from port descriptors ...................................................................... mb/google/skyrim: drop link_hotplug from port descriptors These ports are not hot pluggable, so drop the parameter, which will result it in being set to zero / not enabled. BUG=none TEST=build boot skyrim, verify all PCIe devices functional. Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/73512/1 diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 11748d8..c16041b 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -16,7 +16,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .clk_req = CLK_REQ2, @@ -31,7 +30,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .gpio_group_id = GPIO_27, @@ -47,7 +45,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .gpio_group_id = GPIO_6, -- To view, visit https://review.coreboot.org/c/coreboot/+/73512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Gerrit-Change-Number: 73512 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: device/xhci: Add struct for capability registers
by Felix Held (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Robert Zieba, Raul Rangel, Martin L Roth, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69915 ) Change subject: device/xhci: Add struct for capability registers ...................................................................... Patch Set 13: (1 comment) File src/include/device/xhci.h: https://review.coreboot.org/c/coreboot/+/69915/comment/6660dd82_174cd6c1 PS11, Line 109: > Marking it as packed shouldn't change anything here. […] even in cases where it doesn't change the layout in memory and isn't required, i tend to use __packed to indicate that the resulting memory layout of a struct matters -- To view, visit https://review.coreboot.org/c/coreboot/+/69915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Gerrit-Change-Number: 69915 Gerrit-PatchSet: 13 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 16:44:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2023