coreboot-gerrit March 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/google/skyrim: Allow port descriptors to be overridden
by Martin Roth (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth, Jason Nien, Matt DeVillier, Arthur Heymans, Karthik Ramasubramanian. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73294 ) Change subject: mb/google/skyrim: Allow port descriptors to be overridden ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/73294/comment/ffe81753_ebb1d4cc PS2, Line 97: if (!*dxio_num || !*dxio_descs) : { : *dxio_descs = skyrim_mdn_dxio_descriptors; : *dxio_num = ARRAY_SIZE(skyrim_mdn_dxio_descriptors); : } > Why can't variant instead use the same table and update any of the descriptor elements - eg. […] Sure, we can do that. It's more complex, and I'm not positive it's worth adding that complexity, but if that's what people think we want, we can certainly do that. To do this, I'd create two loops to compare each array entry in the first table with each entry in the second table (if any), and if the start and end lanes are identical then it would be replaced. We'd exit early if we've matched all the lanes in the override table. Is that what you're looking for? So a variant wouldn't be able to bifurcate anything differently if say they wanted to take an NVME lane and use it for a WWAN device. -- To view, visit https://review.coreboot.org/c/coreboot/+/73294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Gerrit-Change-Number: 73294 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 20:19:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Allow port descriptors to be overridden
by Karthik Ramasubramanian (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Martin L Roth, Jason Nien, Matt DeVillier, Arthur Heymans, Martin Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73294 ) Change subject: mb/google/skyrim: Allow port descriptors to be overridden ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/73294/comment/b9d89484_f6dc7cd0 PS2, Line 97: if (!*dxio_num || !*dxio_descs) : { : *dxio_descs = skyrim_mdn_dxio_descriptors; : *dxio_num = ARRAY_SIZE(skyrim_mdn_dxio_descriptors); : } > No, it the compiler won't optimize it out and it won't drop the table above either which is a bigger […] Why can't variant instead use the same table and update any of the descriptor elements - eg. https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he… That way we dont need 2 tables and just operate on a single table. -- To view, visit https://review.coreboot.org/c/coreboot/+/73294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Gerrit-Change-Number: 73294 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 20:00:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITX
by Felix Singer (Code Review) 06 Mar '23

06 Mar '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73097 ) Change subject: mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITX ...................................................................... mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITX This board is based off b75pro3-m, which is very similar. Compared to it, it just lacks a COM1 header, and the secondary ASMedia SATA3 controller. Tested with: CPUs: - Core i5-3330 - Core i5-3470 - Core i7-3770 RAM: - single bank 4GB CL11 - two banks 4+4GB CL9 - two banks 8+8GB CL10 OS: - Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload with embedded default config for boot from USB, disk - UEFI EDK2 payload - Intel ME stripped - Native raminit - Integrated graphics with libgfxinit (HDMI, DVI and VGA) - (boot from) SATA2, SATA3, ports - Rear USB 2 and 3 ports (supports boot) - Internal USB 3.0 ports - Realtek GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS event) Untested: - Internal USB 2.0 ports - eSATA port - 7.1 channel audio Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Change-Id: Ia6a6eb3e922920f4afbcb7828cd2b779b9caebcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73097 Reviewed-by: Kevin Keijzer Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- A src/mainboard/asrock/b75m-itx/Kconfig A src/mainboard/asrock/b75m-itx/Kconfig.name A src/mainboard/asrock/b75m-itx/Makefile.inc A src/mainboard/asrock/b75m-itx/acpi/ec.asl A src/mainboard/asrock/b75m-itx/acpi/platform.asl A src/mainboard/asrock/b75m-itx/acpi/superio.asl A src/mainboard/asrock/b75m-itx/board_info.txt A src/mainboard/asrock/b75m-itx/cmos.default A src/mainboard/asrock/b75m-itx/cmos.layout A src/mainboard/asrock/b75m-itx/data.vbt A src/mainboard/asrock/b75m-itx/devicetree.cb A src/mainboard/asrock/b75m-itx/dsdt.asl A src/mainboard/asrock/b75m-itx/early_init.c A src/mainboard/asrock/b75m-itx/gma-mainboard.ads A src/mainboard/asrock/b75m-itx/gpio.c A src/mainboard/asrock/b75m-itx/hda_verb.c A src/mainboard/asrock/b75m-itx/mainboard.c 17 files changed, 617 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Kevin Keijzer: Looks good to me, but someone else must approve diff --git a/src/mainboard/asrock/b75m-itx/Kconfig b/src/mainboard/asrock/b75m-itx/Kconfig new file mode 100644 index 0000000..51d86f7 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/Kconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_B75M_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6776 + select NO_UART_ON_SUPERIO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asrock/b75m-itx" + +config MAINBOARD_PART_NUMBER + default "B75M-ITX" + +endif diff --git a/src/mainboard/asrock/b75m-itx/Kconfig.name b/src/mainboard/asrock/b75m-itx/Kconfig.name new file mode 100644 index 0000000..40cab89 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_B75M_ITX + bool "B75M-ITX" diff --git a/src/mainboard/asrock/b75m-itx/Makefile.inc b/src/mainboard/asrock/b75m-itx/Makefile.inc new file mode 100644 index 0000000..d1b484d --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += gpio.c +romstage-y += gpio.c + +bootblock-y += early_init.c +romstage-y += early_init.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/b75m-itx/acpi/ec.asl b/src/mainboard/asrock/b75m-itx/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/b75m-itx/acpi/platform.asl b/src/mainboard/asrock/b75m-itx/acpi/platform.asl new file mode 100644 index 0000000..7b1b2b2 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asrock/b75m-itx/acpi/superio.asl b/src/mainboard/asrock/b75m-itx/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/b75m-itx/board_info.txt b/src/mainboard/asrock/b75m-itx/board_info.txt new file mode 100644 index 0000000..a3e8412 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/B75M-ITX/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2012 diff --git a/src/mainboard/asrock/b75m-itx/cmos.default b/src/mainboard/asrock/b75m-itx/cmos.default new file mode 100644 index 0000000..23386fb --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M +cpu_fan_tach_src=CPU_FAN1 diff --git a/src/mainboard/asrock/b75m-itx/cmos.layout b/src/mainboard/asrock/b75m-itx/cmos.layout new file mode 100644 index 0000000..35b4d50 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/cmos.layout @@ -0,0 +1,96 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: mainboard-specific +421 2 e 7 cpu_fan_tach_src + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# cpu_fan_tach_src (select which header provides the tachometer +# signal to the Super I/O on its CPUFANIN input) +7 0 None +7 1 CPU_FAN1 +7 2 CPU_FAN2 +7 3 Both + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asrock/b75m-itx/data.vbt b/src/mainboard/asrock/b75m-itx/data.vbt new file mode 100644 index 0000000..52a8268 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/data.vbt Binary files differ diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb new file mode 100644 index 0000000..9fdad95 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + + device domain 0 on + device pci 00.0 on + subsystemid 0x1849 0x0150 + end + device pci 01.0 on + subsystemid 0x1849 0x0151 + end + device pci 02.0 on + subsystemid 0x1849 0x0152 + end + chip southbridge/intel/bd82x6x + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1849 0x1e31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x1e3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 on # Management Engine KT + subsystemid 0x1849 0x1e3d + end + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x1e2d + end + device pci 1b.0 on # HDA Audio controller + subsystemid 0x1849 0x8892 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1849 0x1e10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x1849 0x1e16 + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6, Realtek PCIe GbE Controller + subsystemid 0x1849 0x1e1a + end + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x1e26 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1e49 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x1c = 0x80 + irq 0x27 = 0xc0 + irq 0x2a = 0x62 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe0 = 0x01 + irq 0xe3 = 0x14 + irq 0xe4 = 0x10 # + enable 3VSBSW# + irq 0xe6 = 0x4c + irq 0xe9 = 0x02 + irq 0xf0 = 0x20 # + pin 70 = 3VSBSW + end + device pnp 2e.b on # HWM, front panel LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on end # GPIO Push-Pull or Open-drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 on end # GPIOA + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1849 0x1e02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x1e22 + end + device pci 1f.5 off end + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/b75m-itx/dsdt.asl b/src/mainboard/asrock/b75m-itx/dsdt.asl new file mode 100644 index 0000000..bce1d9d --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/dsdt.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c new file mode 100644 index 0000000..189e244 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/early_init.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, + {1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6}, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/asrock/b75m-itx/gma-mainboard.ads b/src/mainboard/asrock/b75m-itx/gma-mainboard.ads new file mode 100644 index 0000000..3f217ca --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/b75m-itx/gpio.c b/src/mainboard/asrock/b75m-itx/gpio.c new file mode 100644 index 0000000..a063510 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/gpio.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/b75m-itx/hda_verb.c b/src/mainboard/asrock/b75m-itx/hda_verb.c new file mode 100644 index 0000000..d2824af --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/hda_verb.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18498892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/b75m-itx/mainboard.c b/src/mainboard/asrock/b75m-itx/mainboard.c new file mode 100644 index 0000000..472eb78 --- /dev/null +++ b/src/mainboard/asrock/b75m-itx/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/73097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6a6eb3e922920f4afbcb7828cd2b779b9caebcb Gerrit-Change-Number: 73097 Gerrit-PatchSet: 9 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kevin Keijzer Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/adl: Increase MAX_CPUS to 32 for RPL
by Subrata Banik (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Tim Crawford, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73514 ) Change subject: soc/intel/adl: Increase MAX_CPUS to 32 for RPL ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Gerrit-Change-Number: 73514 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 18:42:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/adl: Increase MAX_CPUS to 32 for RPL
by Tim Crawford (Code Review) 06 Mar '23

06 Mar '23

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73514 ) Change subject: soc/intel/adl: Increase MAX_CPUS to 32 for RPL ...................................................................... soc/intel/adl: Increase MAX_CPUS to 32 for RPL Raptor Lake i9 CPUs have 8P+16E cores for a total of 32 threads. Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/73514/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a8c9aeb..ae5f7a7 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -158,6 +158,7 @@ config MAX_CPUS int + default 32 if SOC_INTEL_RAPTORLAKE default 24 config DCACHE_RAM_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/73514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Gerrit-Change-Number: 73514 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Revert "crossgcc: Upgrade IASL from 20211217 to 20220331"
by Martin L Roth (Code Review) 06 Mar '23

06 Mar '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/64103 ) Change subject: Revert "crossgcc: Upgrade IASL from 20211217 to 20220331" ...................................................................... Abandoned Obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/64103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c1b30585fdfab046a40d1721276d0fa40457a10 Gerrit-Change-Number: 64103 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: Add public gerrit account
by Martin L Roth (Code Review) 06 Mar '23

06 Mar '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51208 ) Change subject: Add public gerrit account ...................................................................... Abandoned Too much potential for abuse. -- To view, visit https://review.coreboot.org/c/coreboot/+/51208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf6d7c47bba10d89956cbb683b8da2e8e04e269d Gerrit-Change-Number: 51208 Gerrit-PatchSet: 4 Gerrit-Owner: Public Gerrit <public-gerrit(a)guerrillamail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Add PM definition for SPR-SP
by Jonathan Zhang (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Johnny Lin, Christian Walter, David Hendricks, Arthur Heymans, Tim Chu. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72613 ) Change subject: soc/intel/xeon_sp: Add PM definition for SPR-SP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992 Gerrit-Change-Number: 72613 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 06 Mar 2023 18:18:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/stoneyridge: request binaryPI to use \_SB_ scope in PSTATE SSDT
by Martin Roth (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73385 ) Change subject: soc/amd/stoneyridge: request binaryPI to use \_SB_ scope in PSTATE SSDT ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/73385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If88820a0f5df923f129e2e3b5335f5f0e38ee7f5 Gerrit-Change-Number: 73385 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Mar 2023 18:00:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/xhci: Add struct for capability registers
by Karthik Ramasubramanian (Code Review) 06 Mar '23

06 Mar '23

Attention is currently required from: Robert Zieba, Raul Rangel, Martin L Roth, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69915 ) Change subject: device/xhci: Add struct for capability registers ...................................................................... Patch Set 13: Code-Review+2 (1 comment) File src/include/device/xhci.h: https://review.coreboot.org/c/coreboot/+/69915/comment/4c2631af_efa6a479 PS11, Line 109: > even in cases where it doesn't change the layout in memory and isn't required, i tend to use __packe […] I had asked for __packed and that comment is addressed. I will mark it as resolved. Please re-open the comment if you feel otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/69915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If38bfde726bd4e5dd314456f25a2b08acd3cd20c Gerrit-Change-Number: 69915 Gerrit-PatchSet: 13 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 06 Mar 2023 17:39:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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