coreboot-gerrit February 2023

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72737 ) Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/72737/1 diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index a4f18a3..59d4043 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_0 on end # GBE + device ref gpp_bridge_2_1 on end # WIFI + device ref gpp_bridge_2_2 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index ec88892..01801ff 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -158,9 +158,9 @@ device domain 0 on device ref iommu on end - device ref gpp_bridge_0 on end # GBE - device ref gpp_bridge_1 on end # WIFI - device ref gpp_bridge_2 on end # NVMe SSD + device ref gpp_bridge_2_0 on end # GBE + device ref gpp_bridge_2_1 on end # WIFI + device ref gpp_bridge_2_2 on end # NVMe SSD device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index e314c39..cd3affa 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -15,12 +15,13 @@ device pci 01.3 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable - device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end - device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end - device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end - device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end - device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end - device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end + device pci 02.1 alias gpp_bridge_2_0 off ops amd_external_pcie_gpp_ops end + device pci 02.2 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end + device pci 02.3 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end + device pci 02.4 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end + device pci 02.5 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end + device pci 02.6 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end + device pci 02.7 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72736 ) Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 ...................................................................... soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/72736/1 diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 5c341c8..e314c39 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -10,6 +10,9 @@ device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 on end # Dummy Host Bridge + device pci 01.1 alias gpp_bridge_1_0 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/72736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Gerrit-Change-Number: 72736 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/*: Hook up GPP bridges ops to devicetree
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68147 ) Change subject: soc/amd/*: Hook up GPP bridges ops to devicetree ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: this introduced a bug on cezanne which is fixed by CB:72735 -- To view, visit https://review.coreboot.org/c/coreboot/+/68147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d Gerrit-Change-Number: 68147 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:34:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72735 ) Change subject: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges ...................................................................... soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree") missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge PCIe root ports, so add them. Those devices were previously covered by the PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that got removed. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 --- M src/soc/amd/cezanne/chipset.cb 1 file changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/72735/1 diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 691153f..c779390 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -8,9 +8,9 @@ device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 on end # Dummy Host Bridge, do not disable - device pci 01.1 alias gpp_gfx_bridge_0 off end - device pci 01.2 alias gpp_gfx_bridge_1 off end - device pci 01.3 alias gpp_gfx_bridge_2 off end + device pci 01.1 alias gpp_gfx_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_gfx_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_gfx_bridge_2 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/72735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Gerrit-Change-Number: 72735 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake: Add a missing RPL-P power limits configuration
by Jérémy Compostella (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Tarun Tuli, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72734 ) Change subject: soc/intel/alderlake: Add a missing RPL-P power limits configuration ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Gerrit-Change-Number: 72734 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:11:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vc/amd/pi: Fix "No such file or directory"
by Eric Lai (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Martin L Roth, Arthur Heymans, Elyes Haouas, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71855 ) Change subject: vc/amd/pi: Fix "No such file or directory" ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Gerrit-Change-Number: 71855 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Add a few missing definitions in iomap.h
by YH Lin (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Subrata Banik, Jérémy Compostella. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72635 ) Change subject: soc/intel/alderlake: Add a few missing definitions in iomap.h ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942 Gerrit-Change-Number: 72635 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:03:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Add a missing RPL-P power limits configuration
by Jérémy Compostella (Code Review) 03 Feb '23

03 Feb '23

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72734 ) Change subject: soc/intel/alderlake: Add a missing RPL-P power limits configuration ...................................................................... soc/intel/alderlake: Add a missing RPL-P power limits configuration This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/alderlake/chip.h 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/72734/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 5173b1c..8e76e55 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -133,6 +133,7 @@ { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, -- To view, visit https://review.coreboot.org/c/coreboot/+/72734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Gerrit-Change-Number: 72734 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
by Eric Lai (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Frank Wu, John Su, Raul Rangel, Ian Feng, Dtrain Hsu, Jason Nien, Jon Murphy, Chris Wang, Martin Roth, Karthik Ramasubramanian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72694 ) Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Gerrit-Change-Number: 72694 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:01:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add chip configuration for I2C devices
by Eric Lai (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Harsha B R, Usha P. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72647 ) Change subject: mb/intel/mtlrvp: Add chip configuration for I2C devices ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5964472be902041f961187c0072a89055badd4f Gerrit-Change-Number: 72647 Gerrit-PatchSet: 3 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:00:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023