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Change subject: vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshake
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
......................................................................
Patch Set 7: Code-Review+2
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Change subject: mb/google/herobrine: Enable early eMMC init in coreboot
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/herobrine/mainboard.c:
https://review.coreboot.org/c/coreboot/+/71830/comment/c6a55e64_37abe8a0
PS8, Line 113: qc_emmc_early_init();
> Excuse my ignorance, but can’t this be controlled by a Kconfig option, and the call be done in the S […]
I think that yes, it could be technically done in the soc code, but I feel like it's much clearer having the initialization call here along with the SD card initialization. This seems to be how MTK is structuring their early emmc init code as well.
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Change subject: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/72051/comment/e090203b_de237d20
PS3, Line 448: # Setting clk_src=2 and clk_req=2 in coreboot,and swap to clk_src=1,clk_req=2 in mFIT
Can you clarify in the comment - "Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping"
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Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72733 )
Change subject: soc/qualcomm/sc7280: Enable pcie device at runtime
......................................................................
soc/qualcomm/sc7280: Enable pcie device at runtime
If we need to initialize pcie on this device (based on sku id), then
enable the pcie device and it's children at runtime.
BUG=b:262586570
BRANCH=None
TEST=Test on a zombie device with NVMe enabled and make sure NVMe
device is enabled.
Change-Id: I6c191e368e54acde919112bbfa966b8d303290a1
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/soc/qualcomm/sc7280/soc.c
1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/72733/1
diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c
index 268f080..72dda24 100644
--- a/src/soc/qualcomm/sc7280/soc.c
+++ b/src/soc/qualcomm/sc7280/soc.c
@@ -7,9 +7,27 @@
#include <soc/cpucp.h>
#include <soc/pcie.h>
+static void sc7280_enable_pci_resources(struct device *dev)
+{
+ struct bus *link;
+ struct device *child;
+
+ if (dev == NULL)
+ return;
+
+ /* If device not enabled, enabled it */
+ dev_set_enabled(dev, 1);
+
+ /* Also enable the children if there are any */
+ for (link = dev->link_list; link; link = link->next)
+ for (child = link->children; child; child = child->sibling)
+ sc7280_enable_pci_resources(child);
+}
+
static struct device_operations pci_domain_ops = {
.read_resources = &qcom_pci_domain_read_resources,
.set_resources = &pci_domain_set_resources,
+ .enable_resources = &sc7280_enable_pci_resources,
.scan_bus = &pci_domain_scan_bus,
.enable = &qcom_setup_pcie_host,
};
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Change subject: mb/google/herobrine: Disable NVMe pci device by default
......................................................................
mb/google/herobrine: Disable NVMe pci device by default
Disable the NVMe pcie device by default. Will submit another CL that
will dynamically enable it at runtime if the NVMe sku is detected.
BUG=b:262586570
BRANCH=None
TEST=boot up and make sure PCI device is disabled.
Change-Id: I539564c9d04bef7600bf04afb095431a06b1810c
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/herobrine/devicetree.cb
1 file changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/72732/1
diff --git a/src/mainboard/google/herobrine/devicetree.cb b/src/mainboard/google/herobrine/devicetree.cb
index 34360b7..61fb96c 100644
--- a/src/mainboard/google/herobrine/devicetree.cb
+++ b/src/mainboard/google/herobrine/devicetree.cb
@@ -3,6 +3,6 @@
chip soc/qualcomm/sc7280
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end
+ device pci 00.0 off end
end
end
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Change subject: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping
......................................................................
Patch Set 3: -Code-Review
(1 comment)
Patchset:
PS3:
> Hi Reka, mind to check this again? it blocks the Craasneto SSD SKU in EVT. […]
Kangheui has been following this so I'll let him comment. Possibly we can submit this to unblock EVT then fix it properly later.
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Change subject: src/sbom/Makefile.inc: Fix variable expansion
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Please rebase on #70251. […]
How are the patches related? My patch does not add any include paths?
The go directory is a current drawback of adding the go programming language into our build. Although it's arguably the same for any language we use in our build system.
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72664 )
Change subject: treewide: Remove unuseful "_ADR: Address" comment
......................................................................
Patch Set 3: Code-Review+1
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Change subject: treewide: Remove unuseful "_UID: Unique ID" comment
......................................................................
Patch Set 3: Code-Review+1
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