coreboot-gerrit February 2023

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[M] Change in coreboot[master]: soc/amd: Use common reset code for PHX & Glinda SoCs
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72754 ) Change subject: soc/amd: Use common reset code for PHX & Glinda SoCs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Gerrit-Change-Number: 72754 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:58:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Use common reset code for CZN & MDN SoCs
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72659 ) Change subject: soc/amd: Use common reset code for CZN & MDN SoCs ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > i agree that making possible reverts easier isn't the strongest argument. […] Split into 3 patches to match the behaviors. - MDN/CZN cold, match existing code - PHX/GLN cold, update the reset behavior - PCO warm -- To view, visit https://review.coreboot.org/c/coreboot/+/72659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Gerrit-Change-Number: 72659 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:58:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Use common reset code for CZN & MDN SoCs
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72659 ) Change subject: soc/amd: Use common reset code for CZN & MDN SoCs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Gerrit-Change-Number: 72659 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:58:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72658 ) Change subject: soc/amd: Create AMD common reset code ...................................................................... Patch Set 2: Code-Review+2 (3 comments) File src/soc/amd/common/block/include/amdblocks/reset.h: https://review.coreboot.org/c/coreboot/+/72658/comment/411f348b_40d9d1df PS1, Line 10: #include <soc/southbridge.h> : : : void do_warm_reset(void); > Thanks, that was a mistake. Done File src/soc/amd/common/block/reset/reset.c: PS1: > There's a lot of stuff that resides in various register blocks just because that's where they put it […] Done https://review.coreboot.org/c/coreboot/+/72658/comment/272eb00b_ff63613f PS1, Line 22: outb(RST_CPU | SYS_RST, RST_CNT); > How about just adding a comment that do_cold_reset() doesn't return? I can't say I really like eithe […] that works for me too -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:58:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Elyes Haouas, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72658 ) Change subject: soc/amd: Create AMD common reset code ...................................................................... Patch Set 2: (4 comments) File src/soc/amd/common/block/include/amdblocks/reset.h: https://review.coreboot.org/c/coreboot/+/72658/comment/f72ffdc6_91b2085d PS1, Line 10: #include <soc/southbridge.h> : : : void do_warm_reset(void); > Thanks, that was a mistake. Done File src/soc/amd/common/block/pm/Makefile.inc: https://review.coreboot.org/c/coreboot/+/72658/comment/e768e984_43acdb29 PS2, Line 4: bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c I originally had this as I did in the original patch: ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_RESET),y) bootblock-y += reset.c verstage_x86-y += reset.c romstage-y += reset.c ramstage-y += reset.c endif I modified it to match the style, but I figure whichever way I do it someone's going to hate it, so I changed it to match the style already in the file. If there's actually a document that indicates the correct style here, I'll change it to match that, otherwise I'm leaving it like this. File src/soc/amd/common/block/reset/reset.c: PS1: > There's a lot of stuff that resides in various register blocks just because that's where they put it […] Moved. https://review.coreboot.org/c/coreboot/+/72658/comment/f5977ef2_aa15d768 PS1, Line 22: outb(RST_CPU | SYS_RST, RST_CNT); > How about just adding a comment that do_cold_reset() doesn't return? I can't say I really like eithe […] Added a comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:56:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya: Create constitution variant
by David Wu (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Tarun Tuli, Matthew Ziegelbaum, Morris Hsu, Nick Vaccaro. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72730 ) Change subject: mb/google/brya: Create constitution variant ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Gerrit-Change-Number: 72730 Gerrit-PatchSet: 2 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pablo Ceballos <pceballos(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Attention: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:52:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: Use common reset code for PCO SoC
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

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[M] Change in coreboot[master]: soc/amd: Use common reset code for PHX & Glinda SoCs
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72754 ) Change subject: soc/amd: Use common reset code for PHX & Glinda SoCs ...................................................................... soc/amd: Use common reset code for PHX & Glinda SoCs This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/glinda/fch.c D src/soc/amd/glinda/reset.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/phoenix/fch.c D src/soc/amd/phoenix/reset.c 8 files changed, 21 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/72754/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 7b0b736..214fc81 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 891a68d..ef0d27d 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -15,19 +15,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -40,7 +37,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index af5f0ec..5608e7c 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -196,6 +197,7 @@ void fch_init(void *chip_info) { + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/glinda/reset.c b/src/soc/amd/glinda/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/glinda/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 883359c..37a2fc9 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 1c24243..84825d0 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -15,19 +15,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -40,7 +37,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index 91df79e..c2f0558 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -192,6 +193,7 @@ void fch_init(void *chip_info) { + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/phoenix/reset.c b/src/soc/amd/phoenix/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/phoenix/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Gerrit-Change-Number: 72754 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd: Use common reset code for CZN & MDN SoCs
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72659 to look at the new patch set (#3). Change subject: soc/amd: Use common reset code for CZN & MDN SoCs ...................................................................... soc/amd: Use common reset code for CZN & MDN SoCs This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fch.c D src/soc/amd/cezanne/reset.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/mendocino/fch.c D src/soc/amd/mendocino/reset.c 8 files changed, 19 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/72659/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Gerrit-Change-Number: 72659 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Elyes Haouas, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72658 to look at the new patch set (#2). Change subject: soc/amd: Create AMD common reset code ...................................................................... soc/amd: Create AMD common reset code This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 --- M src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/common/block/pm/Kconfig M src/soc/amd/common/block/pm/Makefile.inc A src/soc/amd/common/block/pm/reset.c 4 files changed, 70 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/72658/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2023