coreboot-gerrit February 2023

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping
by build bot (Jenkins) (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Henry Sun, Ren Kuo, Tyler Wang, Eric Lai. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72051 ) Change subject: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping ...................................................................... Patch Set 4: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169774): https://review.coreboot.org/c/coreboot/+/72051/comment/6c7ca9c7_349c6bd4 PS4, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) File src/mainboard/google/brya/variants/craask/overridetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169774): https://review.coreboot.org/c/coreboot/+/72051/comment/3f0c8a2a_3feee137 PS4, Line 448: # design.Due to inconsistency between PMC firmware and FSP, we need to set trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/72051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Gerrit-Change-Number: 72051 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 02:05:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
by Frank Wu (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: John Su, Raul Rangel, Ian Feng, Dtrain Hsu, Jason Nien, Jon Murphy, Chris Wang, Martin Roth, Karthik Ramasubramanian. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72694 ) Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hi Google, Could you review the CL? Thank you. Here is the result. https://partnerissuetracker.corp.google.com/issues/260127676#comment22 -- To view, visit https://review.coreboot.org/c/coreboot/+/72694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Gerrit-Change-Number: 72694 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chao Gui <chaogui(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 01:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshake
by Bora Guvendik (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Hannah Williams, Tarun Tuli, Jérémy Compostella. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72693 ) Change subject: vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshake ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892 Gerrit-Change-Number: 72693 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 01:31:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshake
by Bora Guvendik (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Hannah Williams, Tarun Tuli, Jérémy Compostella. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72693 ) Change subject: vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshake ...................................................................... Patch Set 1: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/72693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892 Gerrit-Change-Number: 72693 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 01:31:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/data_fabric_helper: normalize addresses in debug print
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72739 ) Change subject: soc/amd/common/data_fabric_helper: normalize addresses in debug print ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: the ffff in the case of the limit being 0 still looks a bit odd to me, but i'd say that that's the correct decode for those. since the lowest two control bits are both 0, this decide isn't active, so it just looks odd -- To view, visit https://review.coreboot.org/c/coreboot/+/72739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a Gerrit-Change-Number: 72739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 01:22:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Matt DeVillier (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72737 ) Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 01:20:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/data_fabric_helper: normalize addresses in debug print
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72739 ) Change subject: soc/amd/common/data_fabric_helper: normalize addresses in debug print ...................................................................... soc/amd/common/data_fabric_helper: normalize addresses in debug print Instead of just printing the register contents, normalize the contents of the base and limit registers to actual MMIO addresses and then print those. This will hopefully avoid some confusion caused by the shifted addresses. Output on Mandolin before the patch: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Mandolin after the patch: === Data Fabric MMIO configuration registers === idx control base limit 0 93 fc000000 febfffff 1 93 10000000000 ffffffffffff 2 93 d0000000 f7ffffff 3 1093 fed00000 fedfffff 4 90 0 ffff 5 90 0 ffff 6 90 0 ffff 7 90 0 ffff Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a --- M src/soc/amd/common/block/data_fabric/data_fabric_helper.c 1 file changed, 56 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/72739/1 diff --git a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c index 412daae..b64edcd 100644 --- a/src/soc/amd/common/block/data_fabric/data_fabric_helper.c +++ b/src/soc/amd/common/block/data_fabric/data_fabric_helper.c @@ -47,16 +47,23 @@ void data_fabric_print_mmio_conf(void) { + uint32_t control; + uint64_t base, limit; printk(BIOS_SPEW, "=== Data Fabric MMIO configuration registers ===\n" - "Addresses are shifted to the right by 16 bits.\n" - "idx control base limit\n"); + "idx control base limit\n"); for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) { - printk(BIOS_SPEW, " %2u %8x %8x %8x\n", - i, - data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)), - data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)), - data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i))); + control = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i)); + /* Base and limit address registers don't contain the lower address bits, but + are shifted by D18F0_MMIO_SHIFT bits */ + base = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_BASE(i)) + << D18F0_MMIO_SHIFT; + limit = (uint64_t)data_fabric_broadcast_read32(0, NB_MMIO_LIMIT(i)) + << D18F0_MMIO_SHIFT; + /* Lower D18F0_MMIO_SHIFT address limit bits are all 1 */ + limit += (1 << D18F0_MMIO_SHIFT) - 1; + printk(BIOS_SPEW, " %2u %8x %16llx %16llx\n", + i, control, base, limit); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/72739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a Gerrit-Change-Number: 72739 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
by Matt DeVillier (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72736 ) Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Gerrit-Change-Number: 72736 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 01:19:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72735 to look at the new patch set (#2). Change subject: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges ...................................................................... soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree") missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge PCIe ports, so add them. Those devices were previously covered by the PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that got removed in the referenced commit. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 --- M src/soc/amd/cezanne/chipset.cb 1 file changed, 19 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/72735/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Gerrit-Change-Number: 72735 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd: Use common reset code for PCO SoC
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Martin L Roth, Matt DeVillier, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72755 ) Change subject: soc/amd: Use common reset code for PCO SoC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735 Gerrit-Change-Number: 72755 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 00:59:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023