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Change subject: [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Hi Jeremy, curious how much of this worked? e.g. […]
The libgfxinit partially runs but does not even get to the read EDID stage. There are some clock configuration changes to perform and more importantly the power domain configuration register seems to not work the way they used to.
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Change subject: [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life
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Patch Set 1:
(1 comment)
Patchset:
PS1:
> We shall first enable libgfxinit instead GFX PEIM as first phase before enabling early SOL. […]
Are you actively working on this ?
In my action list, I also wanted to enable libgfxinit in ramstage. The idea being to not waste time in issues which could be related to running it before FSP on MTL. I created https://review.coreboot.org/c/coreboot/+/72731 for this. libgfxinit does not execute a lot better in ramstage than in romstage. Some Adaptation for gen12+ is clearly necessary.
Anil will be leading this activity as I have to focus on another topic.
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Change subject: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71715/comment/c0b356e2_7655d700
PS3, Line 10: Setting this GPIO to 1 or 0 will not change the GPIO
: configuration
> I just used `inteltool`. […]
`inteltool` would have to know *all* GPIOs to reliably show a difference.
But like I said, just a thought. That Google has a private FSP (once more)
is as likely as `inteltool` failing.
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Change subject: soc/intel: Use common codeflow for MP init
......................................................................
Patch Set 3: Code-Review+1
(2 comments)
Patchset:
PS3:
+2
File src/soc/intel/alderlake/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/72604/comment/e5685d6c_8daadf66
PS3, Line 25: romstage-y += cpu.c
I've confirmed that the binary doesn't change (one can't be too careful
with soc/intel/ and its `weak`ness).
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Change subject: soc/intel/apl: Hook up cpu ops in devicetree
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Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72705/comment/9944e7a0_0ee21bd7
PS1, Line 10: afterwards
Sounds odd, did you mean 'before'?
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Change subject: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
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Patch Set 21: Code-Review+2
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Change subject: util/cbfstool: Add eventLog support for ELOG_TYPE_FW_EARLY_SOL
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Patch Set 14: Code-Review+2
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Change subject: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type
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Patch Set 9: Code-Review+2
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