coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: security/vboot: Don't build with flashrom support
by Brian Norris (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Julius Werner, Yu-Ping Wu. Brian Norris has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72716 ) Change subject: security/vboot: Don't build with flashrom support ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: looks like I can't submit changes here. Jack, Raul, one of you want to? -- To view, visit https://review.coreboot.org/c/coreboot/+/72716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53bcc2d1e7666646ddad58ba3717cfdd321014e8 Gerrit-Change-Number: 72716 Gerrit-PatchSet: 4 Gerrit-Owner: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Jack Rosenthal <jrosenth(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 02 Feb 2023 16:43:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/qualcomm/common: Add sdhci_msm_init function
by Shelley Chen (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: mturney mturney, Julius Werner, Sudheer Amrabadi. Hello build bot (Jenkins), mturney mturney, Julius Werner, Sudheer Amrabadi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72634 to look at the new patch set (#4). Change subject: soc/qualcomm/common: Add sdhci_msm_init function ...................................................................... soc/qualcomm/common: Add sdhci_msm_init function Porting from depthcharge changes for supporting eMMC driver functionality with standard SDHC controller on Qualcomm chipsets. sdhci_msm_init() needs to be run before the standard sdhci_mem_controller initiailzation. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/soc/qualcomm/common/include/soc/sdhci_msm.h A src/soc/qualcomm/common/storage/sdhci_msm.c 2 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/72634/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Gerrit-Change-Number: 72634 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/qualcomm/common: Add sdhci_msm_init function
by Shelley Chen (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: mturney mturney, Julius Werner, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72634 ) Change subject: soc/qualcomm/common: Add sdhci_msm_init function ...................................................................... Patch Set 3: (2 comments) File src/soc/qualcomm/common/include/soc/sdhci_msm.h: https://review.coreboot.org/c/coreboot/+/72634/comment/051ccc2e_f7fe6e0d PS2, Line 54: #define CMDIN_RCLK_EN (1 << 1) > I don't think we need all of these definitions? Yeah, you're right. I'll clean out the ones that we're not using. File src/soc/qualcomm/common/storage/sdhci_msm.c: https://review.coreboot.org/c/coreboot/+/72634/comment/ed8f6905_29c50a07 PS2, Line 64: if (host == NULL) > I think this can be simplified to a one-liner. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Gerrit-Change-Number: 72634 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Thu, 02 Feb 2023 16:38:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/qualcomm/common: Add sdhci_msm_init function
by Shelley Chen (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Shelley Chen, mturney mturney, Sudheer Amrabadi. Hello build bot (Jenkins), mturney mturney, Julius Werner, Sudheer Amrabadi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72634 to look at the new patch set (#3). Change subject: soc/qualcomm/common: Add sdhci_msm_init function ...................................................................... soc/qualcomm/common: Add sdhci_msm_init function Porting from depthcharge changes for supporting eMMC driver functionality with standard SDHC controller on Qualcomm chipsets. sdhci_msm_init() needs to be run before the standard sdhci_mem_controller initiailzation. BUG=b:254092907 BRANCH=None TEST=emerge-herobrine coreboot Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/soc/qualcomm/common/include/soc/sdhci_msm.h A src/soc/qualcomm/common/storage/sdhci_msm.c 2 files changed, 102 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/72634/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0 Gerrit-Change-Number: 72634 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya: Create constitution variant
by Pablo Ceballos (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Matthew Ziegelbaum, Morris Hsu, Nick Vaccaro. Pablo Ceballos has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72730 ) Change subject: mb/google/brya: Create constitution variant ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Gerrit-Change-Number: 72730 Gerrit-PatchSet: 2 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pablo Ceballos <pceballos(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Attention: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 02 Feb 2023 16:00:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
by Paul Fagerburg (Code Review) 02 Feb '23

02 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71882 ) Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table ...................................................................... mb/google/dedede/var/dibbi: Update devicetree and GPIO table Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:260934185, b:260934719 BRANCH=dedede TEST=build Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882 Reviewed-by: Adam Mills <adamjmills(a)google.com> Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/dibbi/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/gpio.c M src/mainboard/google/dedede/variants/dibbi/overridetree.cb 4 files changed, 314 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved Adam Mills: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index eeed1aa..eb69198 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -11,6 +11,9 @@ config BOARD_GOOGLE_DIBBI bool "-> Dibbi" select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE config BOARD_GOOGLE_DEDEDE bool "-> Dedede" diff --git a/src/mainboard/google/dedede/variants/dibbi/Makefile.inc b/src/mainboard/google/dedede/variants/dibbi/Makefile.inc new file mode 100644 index 0000000..eb2c9bc --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/dibbi/gpio.c b/src/mainboard/google/dedede/variants/dibbi/gpio.c new file mode 100644 index 0000000..f1a6516 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/gpio.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + /* A12 : USB_OC1_N */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : USB_OC2_N */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : USB_OC3_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A18 : USB_OC0_N */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D4 : LAN_PE_ISOLATE_ODL_R */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* D17 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + + /* E13 : GPP_E13/DDI0_DDC_SCL */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14 : GPP_E14/DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : GPP_E15/DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + /* E16 : GPP_E16/DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* H15 : I2S_SPK_BCLK */ + PAD_NC(GPP_H15, NONE), + + /* R6 : I2S_SPK_LRCK */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_SPK_AUDIO */ + PAD_NC(GPP_R7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), + /* S6 : DMIC0_CLK */ + PAD_NC(GPP_S6, NONE), + /* S7 : DMIC0_DATA */ + PAD_NC(GPP_S7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb index 404024b..a017307 100644 --- a/src/mainboard/google/dedede/variants/dibbi/overridetree.cb +++ b/src/mainboard/google/dedede/variants/dibbi/overridetree.cb @@ -8,10 +8,6 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | Trackpad | - #| I2C1 | Digitizer | - #| I2C2 | Touchscreen | - #| I2C3 | Camera | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -19,24 +15,202 @@ .speed_mhz = 1, .early_init = 1, }, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, }, }" + # Enable Root Port 3 (index 2) for LAN + # External PCIe port 7 is mapped to PCIe Root Port 3 + register "PcieRpEnable[2]" = "1" + register "PcieClkSrcUsage[4]" = "2" + + # Enable Root Port 7 (index 6) for WLAN + # External PCIe port 3 is mapped to PCIe Root Port 7 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + + # Disable PCIe Root Port 8 + register "PcieRpEnable[7]" = "0" + + # Audio related configurations + register "PchHdaAudioLinkDmicEnable[0]" = "0" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + + # Disable SD card + register "sdcard_cd_gpio" = "0" + register "SdCardPowerEnableActiveHigh" = "0" + + # Disable eDP on port A + register "DdiPortAConfig" = "0" + + # Enable HPD and DDC for DDI port A + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "1" + + # USB Port Configuration + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # No USB3/2 Type-C Port C1 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 + device domain 0 on - device pci 15.0 on end + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN) + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 100, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Power"" + register "options.tsr[2].desc" = ""Chassis"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + # TODO (b/264960828) verify PLD values + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 4)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 5)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + device usb 3.1 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 4)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 5)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C 4 + device pci 1c.2 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW0_03" # GPP_B3 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + register "device_index" = "0" + device pci 00.0 on end + end + end # PCI Express Root Port 3 - RTL8111H LAN + device pci 1c.6 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 7 - WLAN + device pci 1c.7 off end # PCI Express Root Port 8 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/71882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Gerrit-Change-Number: 71882 Gerrit-PatchSet: 7 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constant
by Paul Fagerburg (Code Review) 02 Feb '23

02 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72653 ) Change subject: drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constant ...................................................................... drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constant Contents of the EDID are passed by a reference to an array of length 0x80, for which the macro 'PTN_EDID_LEN' has already been around. This patch makes use of this macro within the driver and mainboard implementation utilizing it. BUG=none TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards. Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/drivers/i2c/ptn3460/ptn3460.c M src/drivers/i2c/ptn3460/ptn3460.h M src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c M src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c 7 files changed, 30 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/drivers/i2c/ptn3460/ptn3460.c b/src/drivers/i2c/ptn3460/ptn3460.c index 31db8ad..d2df04d 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.c +++ b/src/drivers/i2c/ptn3460/ptn3460.c @@ -123,7 +123,7 @@ init_done = true; } -__weak enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +__weak enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { return CB_ERR; } diff --git a/src/drivers/i2c/ptn3460/ptn3460.h b/src/drivers/i2c/ptn3460/ptn3460.h index 5d867cd..ecd2191 100644 --- a/src/drivers/i2c/ptn3460/ptn3460.h +++ b/src/drivers/i2c/ptn3460/ptn3460.h @@ -52,7 +52,7 @@ /* We need functions which we can call to get mainboard specific data */ /* These functions can be implemented somewhere else but must exist. */ -extern enum cb_err mb_get_edid(uint8_t edid_data[0x80]); +extern enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]); extern uint8_t mb_select_edid_table(void); extern enum cb_err mb_adjust_cfg(struct ptn_3460_config *cfg_ptr); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c index 0fce19c..8a20f36 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c index d5de17d..39cc274 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c index 348f762..c74e90a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c @@ -33,7 +33,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c index d5de17d..39cc274 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c index 7b16254..316eb71 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl3/lcd_panel.c @@ -10,7 +10,7 @@ * @param edid_data pointer to EDID data in driver * @return CB_SUCCESS on successful EDID data retrieval, CB_ERR otherwise */ -enum cb_err mb_get_edid(uint8_t edid_data[0x80]) +enum cb_err mb_get_edid(uint8_t edid_data[PTN_EDID_LEN]) { const char *hwi_block = "hwinfo.hex"; -- To view, visit https://review.coreboot.org/c/coreboot/+/72653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962 Gerrit-Change-Number: 72653 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
by Michał Żygowski (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Sean Rhodes, Nico Huber, Tarun Tuli, Subrata Banik, Paul Menzel, Arthur Heymans, Eric Lai. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71715 ) Change subject: soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetree ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > SDI1 doesn't make any difference to me. […] @Eric the SDI GPIOs is not the only point that ensures proper HDA operation. In the mentioned PeiCavsInitLib there is a line: HdaCallbacks->HdaPcrPidDspAndThenOr32 (R_HDA_PCR_CDCCFG, (UINT32)~0, (B_HDA_PCR_CDCCFG_DIS_SDIN0 | B_HDA_PCR_CDCCFG_DIS_SDIN1)); that will be executed if (HdaPreMemConfig->AudioLinkHda.Enable == FALSE) else if (HdaPreMemConfig->AudioLinkHda.Enable == TRUE) AND (HdaPreMemConfig->AudioLinkHda.SdiEnable[0] == FALSE) then HdaCallbacks->HdaPcrPidDspAndThenOr32 (R_HDA_PCR_CDCCFG, (UINT32)~0, (B_HDA_PCR_CDCCFG_DIS_SDIN0)); is executed, effectively disabling SDI pins in the HDA private configuration space. To be clear: HdaPreMemConfig->AudioLinkHda.Enable = FspmUpd->FspmConfig.PchHdaAudioLinkHdaEnable; HdaPreMemConfig->AudioLinkHda.SdiEnable[Index] = FspmUpd->FspmConfig.PchHdaSdiEnable[Index]; That is why we need PchHdaAudioLinkHdaEnable and PchHdaSdiEnable to be board-controllable. By default PchHdaSdiEnable[0] and PchHdaAudioLinkHdaEnable UPDs are set to enabled, but coreboot overrides them to disabled in soc code, which make HDA non-functional in my and Sean's cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/71715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Gerrit-Change-Number: 71715 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Feb 2023 15:51:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Martin L Roth (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Elyes Haouas, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72658 ) Change subject: soc/amd: Create AMD common reset code ...................................................................... Patch Set 1: (3 comments) File src/soc/amd/common/block/include/amdblocks/reset.h: https://review.coreboot.org/c/coreboot/+/72658/comment/b0b60466_bb9b81b6 PS1, Line 10: #include <soc/southbridge.h> : : : void do_warm_reset(void); > maybe just one empty line? Thanks, that was a mistake. File src/soc/amd/common/block/reset/reset.c: PS1: > since this lives in the acpimmio pm register block, i'd consider moving it to soc/amd/common/block/p […] There's a lot of stuff that resides in various register blocks just because that's where they put it. By this argument, should everything that goes under the LPC registers go into the LPC block? SPI for example? I think we can all agree that doing that doesn't make sense. I'll move it if that's really the preference, but at that point, does the reset get its own config option, or does it use the SOC_AMD_COMMON_BLOCK_PM option? If it gets it's own option, i think that's another reason to keep it in a separate directory. https://review.coreboot.org/c/coreboot/+/72658/comment/e4909a15_e68fa6bd PS1, Line 22: outb(RST_CPU | SYS_RST, RST_CNT); > i'd either put this into the corresponding else branch or add a return after the do_cold_reset call. […] How about just adding a comment that do_cold_reset() doesn't return? I can't say I really like either of the above options. -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Feb 2023 15:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Enable HPD GPIO
by Matt DeVillier (Code Review) 02 Feb '23

02 Feb '23

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72431 ) Change subject: mb/starlabs/starbook/adl: Enable HPD GPIO ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Gerrit-Change-Number: 72431 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 02 Feb 2023 15:45:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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