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Change in coreboot[master]: [TEST] Add support for link time optimization
by Jacob Garber (Code Review) 22 Feb '24

22 Feb '24

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38989 ) Change subject: [TEST] Add support for link time optimization ...................................................................... [TEST] Add support for link time optimization - Code generation is not done until after linking, so the compiler must be invoked at all linking stages instead of the linker. As a consequence all linker arguments must be prefixed with -Wl. - Partial linking is not supported. Instead, object files are collected into thin archives that are linked instead. - The dead_code() macro causes linking errors, since dead functions aren't optimized out until after linking has begun. This macro could be replaced with the preprocessor if necessary, or just disabled for LTO builds. - Wrapping libgcc functions causes a symbol mismatch when using LTO. Wrapping these functions was originally done to support alternate regparam values, though AFAICT this isn't used anywhere. Using LTO leads to a ~10% decrease in stage size for QEMU and ~18% for the Thinkpad T500, and both targets boot successfully. Change-Id: I48c31ea8b1b57276125cffdac44c7c16642547ac Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile.inc M src/Kconfig M src/arch/x86/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/include/assert.h M src/lib/Makefile.inc M src/lib/gcc.c M toolchain.inc M util/xcompile/xcompile 9 files changed, 42 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/38989/1 diff --git a/Makefile.inc b/Makefile.inc index 1f18726..b85c11b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -434,6 +434,10 @@ endif endif +ifeq ($(CONFIG_LTO),y) +CFLAGS_common += -flto -fuse-linker-plugin -fno-fat-lto-objects +endif + ADAFLAGS_common += -gnatp ADAFLAGS_common += -Wuninitialized -Wall -Werror ADAFLAGS_common += -pipe -g -nostdinc @@ -478,7 +482,7 @@ # Disable style checks for now ADAFLAGS_common += -gnatyN -LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +LDFLAGS_common := -nostdlib -nostartfiles -static -Wl,--emit-relocs,--gc-sections ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror diff --git a/src/Kconfig b/src/Kconfig index f75f942..4b81818 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -116,6 +116,15 @@ For details see https://ccache.samba.org. +config LTO + bool "Use link time optimization" + # Enable now for testing + default y + depends on COMPILER_GCC + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config FMD_GENPARSER bool "Generate flashmap descriptor parser using flex and bison" default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 534f2ce..75f96d2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -80,7 +80,7 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" - $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) --oformat $(2) + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) -Wl,--whole-archive,--start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) -Wl,--no-whole-archive $$(COMPILER_RT_$(1)) -Wl,--end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) -Wl,--oformat=$(2) -LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders >/dev/null 2>&1 if [ -z "$$$$($$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders 2>&1 | grep 'no symbols')" ];then \ echo "Forbidden global variables in $(1):"; \ @@ -212,11 +212,11 @@ postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c -LDFLAGS_postcar += -Map $(objcbfs)/postcar.map +LDFLAGS_postcar += -Wl,-Map,$(objcbfs)/postcar.map $(objcbfs)/postcar.debug: $$(postcar-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) -Wl,--whole-archive,--start-group $(filter-out %.ld,$^) -Wl,--no-whole-archive $(COMPILER_RT_postcar) -Wl,--end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ @@ -309,18 +309,20 @@ endif -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) - -$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) - @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group +LDFLAGS_ramstage += -Wl,-m,elf_i386 else - $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group +LDFLAGS_ramstage += -Wl,-m,elf_x86_64 endif +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.a $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) $(COMPILER_RT_FLAGS_ramstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $< -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group -T $(call src-to-obj,ramstage,src/arch/x86/memlayout.ld) + +$(objgenerated)/ramstage.a: $$(ramstage-objs) $$(ramstage-libs) + @printf " AR $(subst $(obj)/,,$(@))\n" + $(AR_ramstage) rcT $@ $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) + endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..f582a31 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -25,8 +25,8 @@ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) -$(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group +$(obj)/smm/smm.a: $$(smm-objs) + $(AR_smm) rcT $@ $^ # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -53,7 +53,7 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) - $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) -Wl,--whole-archive,--start-group $(smmstub-objs) -Wl,--no-whole-archive $(COMPILER_RT_smmstub) -Wl,--end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) @@ -72,9 +72,9 @@ # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) else -$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.a, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif $(obj)/smm/smm: $(obj)/smm/smm.elf.rmod @@ -82,8 +82,8 @@ else # CONFIG_SMM_TSEG -$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o +$(obj)/smm/smm: $(obj)/smm/smm.a $(src)/cpu/x86/smm/smm.ld + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld -Wl,--whole-archive,--start-group $(obj)/smm/smm.a -Wl,--no-whole-archive $(COMPILER_RT_smm) --end-group $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ diff --git a/src/include/assert.h b/src/include/assert.h index e0db0bc..6901953 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -61,7 +61,8 @@ dead_code_assertion_failed_at_line_##line(); \ } while (0) #define _dead_code(line) __dead_code(line) -#define dead_code() _dead_code(__LINE__) +//#define dead_code() _dead_code(__LINE__) +#define dead_code() /* This can be used in the context of an expression of type 'type'. */ #define dead_code_t(type) ({ \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2333f64..ac6d624 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -291,7 +291,7 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--no-whole-archive $$(COMPILER_RT_rmodules_$(4)) -Wl,--end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map endef diff --git a/src/lib/gcc.c b/src/lib/gcc.c index 5a93f45..66a7788 100644 --- a/src/lib/gcc.c +++ b/src/lib/gcc.c @@ -24,6 +24,7 @@ /* TODO: maybe this code should move to arch/x86 as architecture * specific implementations may vary */ +#if 0 #define WRAP_LIBGCC_CALL(type, name) \ asmlinkage type __real_##name(type a, type b); \ type __wrap_##name(type a, type b); \ @@ -33,3 +34,4 @@ WRAP_LIBGCC_CALL(unsigned long long, __udivdi3) WRAP_LIBGCC_CALL(long long, __moddi3) WRAP_LIBGCC_CALL(unsigned long long, __umoddi3) +#endif diff --git a/toolchain.inc b/toolchain.inc index 865227b..f52a518 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -117,7 +117,7 @@ $(error Check your .config file for CONFIG_ARCH_$(1)_* settings)) CC_$(1) := $(CC_$(2)) GCC_$(1) := $(GCC_CC_$(2)) -LD_$(1) := $(LD_$(2)) +LD_$(1) := $(CC_$(2)) NM_$(1) := $(NM_$(2)) AR_$(1) := $(AR_$(2)) GNATBIND_$(1) := $(GNATBIND_$(2)) @@ -130,7 +130,7 @@ CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) -D__ARCH_$(2)__ COMPILER_RT_$(1) := $$(COMPILER_RT_$(2)) COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2)) -LDFLAGS_$(1) = $$(LDFLAGS_common) $$(LDFLAGS_$(2)) +LDFLAGS_$(1) = $$(CFLAGS_$(1)) $$(LDFLAGS_common) $$(LDFLAGS_$(2)) endef # define_class: Allows defining any program as dynamic class and compiler tool diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 3203d71..8515813 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -363,7 +363,7 @@ TCLIST="i386 x86_64" TWIDTH="32" TABI="elf" - CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3" + #CC_RT_EXTRA_GCC="-Wl,--wrap=__divdi3,--wrap=__udivdi3,--wrap=__moddi3,--wrap=__umoddi3" } arch_config_ppc64() { -- To view, visit https://review.coreboot.org/c/coreboot/+/38989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48c31ea8b1b57276125cffdac44c7c16642547ac Gerrit-Change-Number: 38989 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

9 34

Change in coreboot[master]: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM
by Arthur Heymans (Code Review) 20 Feb '24

20 Feb '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37198 ) Change subject: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM ...................................................................... nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM AGESA sets up MTRR's to cache the whole dram, so decompressing postcar stage to cbmem should be fast and is now selected by default. Change-Id: I62ffe1bd646e9ddad77be240f030601790f4da4b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/agesa/family14/Kconfig M src/northbridge/amd/agesa/family15tn/Kconfig M src/northbridge/amd/agesa/family16kb/Kconfig 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/37198/1 diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 173714f..cfafb23 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY14 bool + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_AMD_AGESA_FAMILY14 diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index a0841eb..e6a469f 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY15_TN bool + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/northbridge/amd/agesa/family16kb/Kconfig b/src/northbridge/amd/agesa/family16kb/Kconfig index 2be2fd3..e34ef60 100644 --- a/src/northbridge/amd/agesa/family16kb/Kconfig +++ b/src/northbridge/amd/agesa/family16kb/Kconfig @@ -15,6 +15,7 @@ ## config NORTHBRIDGE_AMD_AGESA_FAMILY16_KB bool + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_AMD_AGESA_FAMILY16_KB -- To view, visit https://review.coreboot.org/c/coreboot/+/37198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62ffe1bd646e9ddad77be240f030601790f4da4b Gerrit-Change-Number: 37198 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: sb/intel/bd82x6x: Rework PCH ID cache
by Angel Pons (Code Review) 18 Jan '24

18 Jan '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 ) Change subject: sb/intel/bd82x6x: Rework PCH ID cache ...................................................................... sb/intel/bd82x6x: Rework PCH ID cache Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore. Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/common.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1 diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 7480174..0094db6 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -13,9 +13,9 @@ int pch_silicon_revision(void) { - static int pch_revision_id = -1; + static int pch_revision_id = 0; - if (pch_revision_id < 0) + if (!pch_revision_id) pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); return pch_revision_id; @@ -23,9 +23,9 @@ int pch_silicon_type(void) { - static int pch_type = -1; + static int pch_type = 0; - if (pch_type < 0) + if (!pch_type) pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); return pch_type; -- To view, visit https://review.coreboot.org/c/coreboot/+/49168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Gerrit-Change-Number: 49168 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: sb/intel/bd82x6x/pch.c: Extract common functions
by Angel Pons (Code Review) 18 Jan '24

18 Jan '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49167 ) Change subject: sb/intel/bd82x6x/pch.c: Extract common functions ...................................................................... sb/intel/bd82x6x/pch.c: Extract common functions PCH identification functions and `pch_iobp_update` are used in multiple stages. Move them out of `pch.c` to drop some ugly preprocessor usage. Subsequent commits will use `pch_iobp_update` in romstage as well. Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc A src/southbridge/intel/bd82x6x/common.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h 4 files changed, 122 insertions(+), 119 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/49167/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 687fc97..469a50e 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -7,6 +7,7 @@ ramstage-y += pch.c ramstage-y += azalia.c +ramstage-y += common.c ramstage-y += fadt.c ramstage-y += lpc.c ramstage-y += pci.c @@ -26,8 +27,9 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c +smm-y += common.c smihandler.c me.c me_8.x.c me_common.c +romstage-y += common.c romstage-y += me_status.c romstage-y += early_rcba.c romstage-y += early_pch.c diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c new file mode 100644 index 0000000..7480174 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/common.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <stdint.h> + +#include "pch.h" + +int pch_silicon_revision(void) +{ + static int pch_revision_id = -1; + + if (pch_revision_id < 0) + pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); + + return pch_revision_id; +} + +int pch_silicon_type(void) +{ + static int pch_type = -1; + + if (pch_type < 0) + pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1); + + return pch_type; +} + +int pch_silicon_supported(int type, int rev) +{ + int cur_type = pch_silicon_type(); + int cur_rev = pch_silicon_revision(); + + switch (type) { + case PCH_TYPE_CPT: + /* CougarPoint minimum revision */ + if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) + return 1; + /* PantherPoint any revision */ + if (cur_type == PCH_TYPE_PPT) + return 1; + break; + + case PCH_TYPE_PPT: + /* PantherPoint minimum revision */ + if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) + return 1; + break; + } + + return 0; +} + +#define IOBP_RETRY 1000 +static inline int iobp_poll(void) +{ + unsigned int try = IOBP_RETRY; + u32 data; + + while (try--) { + data = RCBA32(IOBPS); + if ((data & 1) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP timeout\n"); + return 0; +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_READ_AX; + if (!iobp_poll()) + return; + + /* Read IOBP data */ + data = RCBA32(IOBPD); + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + if ((RCBA32(IOBPS) & 0x6) != 0) { + printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); + return; + } + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + /* WRITE OPCODE */ + if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) + RCBA32(IOBPS) = IOBPS_RW_BX; + else + RCBA32(IOBPS) = IOBPS_WRITE_AX; + if (!iobp_poll()) + return; + + /* Write IOBP data */ + RCBA32(IOBPD) = data; + if (!iobp_poll()) + return; +} diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 82b95f6..1c8786d 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -11,123 +11,6 @@ #include "chip.h" #include "pch.h" -int pch_silicon_revision(void) -{ - static int pch_revision_id = -1; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = pcidev_on_root(0x1f, 0); -#endif - - if (pch_revision_id < 0) - pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); - return pch_revision_id; -} - -int pch_silicon_type(void) -{ - static int pch_type = -1; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else - struct device *dev = pcidev_on_root(0x1f, 0); -#endif - - if (pch_type < 0) - pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); - return pch_type; -} - -static int pch_silicon_supported(int type, int rev) -{ - int cur_type = pch_silicon_type(); - int cur_rev = pch_silicon_revision(); - - switch (type) { - case PCH_TYPE_CPT: - /* CougarPoint minimum revision */ - if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) - return 1; - /* PantherPoint any revision */ - if (cur_type == PCH_TYPE_PPT) - return 1; - break; - - case PCH_TYPE_PPT: - /* PantherPoint minimum revision */ - if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) - return 1; - break; - } - - return 0; -} - -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned int try = IOBP_RETRY; - u32 data; - - while (try--) { - data = RCBA32(IOBPS); - if ((data & 1) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP timeout\n"); - return 0; -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_READ_AX; - if (!iobp_poll()) - return; - - /* Read IOBP data */ - data = RCBA32(IOBPD); - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - if ((RCBA32(IOBPS) & 0x6) != 0) { - printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); - return; - } - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - /* WRITE OPCODE */ - if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) - RCBA32(IOBPS) = IOBPS_RW_BX; - else - RCBA32(IOBPS) = IOBPS_WRITE_AX; - if (!iobp_poll()) - return; - - /* Write IOBP data */ - RCBA32(IOBPD) = data; - if (!iobp_poll()) - return; -} - -#ifndef __SIMPLE_DEVICE__ /* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned int devfn) { @@ -426,4 +309,3 @@ CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") .enable_dev = pch_enable, }; -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1840a2b..dcab839 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -42,6 +42,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/49167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab Gerrit-Change-Number: 49167 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: nb/intel/sandybridge: Refine power-down mode logic
by Angel Pons (Code Review) 04 Jan '24

04 Jan '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47746 ) Change subject: nb/intel/sandybridge: Refine power-down mode logic ...................................................................... nb/intel/sandybridge: Refine power-down mode logic When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 3 files changed, 41 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47746/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..9cd522f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -99,6 +99,15 @@ hex default 0x0 +config RAMINIT_ALWAYS_ALLOW_DLL_OFF + bool "Also enable memory DLL-off mode on desktops and servers" + default n + help + If enabled, allow enabling DLL-off mode for platforms other than + mobile. Saves power at the expense of higher exit latencies. Has + no effect on mobile platforms, where DLL-off is always allowed. + Power down is disabled for stability when running at high clocks. + config RAMINIT_ENABLE_ECC bool "Enable ECC if supported" default y diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b06734c..d533ca8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -688,11 +688,29 @@ iosav_run_once(channel); } +/* Obtain optimal power down mode for current configuration */ +static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) +{ + if (ctrl->tXP > 8) + return PDM_NONE; + + if (ctrl->tXPDLL > 32) + return PDM_PPD; + + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) + return PDM_DLL_OFF; + + return PDM_APD_PPD; +} + static u32 make_mr0(ramctr_timing *ctrl, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; + + const enum pdwm_mode power_down = get_power_down_mode(ctrl); + + const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { @@ -712,8 +730,8 @@ mr0reg |= (mch_cas & 0xe) << 3; mr0reg |= mch_wr << 9; - /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg |= !is_mobile << 12; + /* Precharge PD - Use slow exit when DLL-off is used - mostly power-saving feature */ + mr0reg |= !slow_exit << 12; return mr0reg; } @@ -2830,8 +2848,6 @@ /* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { - const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; - int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; @@ -2848,12 +2864,8 @@ MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; } - if (is_mobile) - /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; - else - /* APD - PPD, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; + /* 64 DCLKs until idle, decision per rank */ + MCHBAR32(PM_PDWN_CONFIG) = get_power_down_mode(ctrl) << 8 | 64; FOR_ALL_CHANNELS MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 050aa70..80d3074 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -273,6 +273,15 @@ */ #define MRC_CACHE_VERSION 5 +enum pdwm_mode { + PDM_NONE = 0, + PDM_APD = 1, + PDM_PPD = 2, + PDM_APD_PPD = 3, + PDM_DLL_OFF = 6, + PDM_APD_DLL_OFF = 7, +}; + typedef struct odtmap_st { u16 rttwr; u16 rttnom; -- To view, visit https://review.coreboot.org/c/coreboot/+/47746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Gerrit-Change-Number: 47746 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

[XS] Change in coreboot[main]: drivers/smmstore/ramstage: use pm_acpi_smi_cmd_port
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79766?usp=email ) Change subject: drivers/smmstore/ramstage: use pm_acpi_smi_cmd_port ...................................................................... drivers/smmstore/ramstage: use pm_acpi_smi_cmd_port Use pm_acpi_smi_cmd_port() to get the APMC trigger IO port instead of using the hard-coded APM_CNT define. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 --- M src/drivers/smmstore/ramstage.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/79766/1 diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index ef80e22..3804c0f 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -36,6 +36,7 @@ static void init_store(void *unused) { + const uint16_t apmc_port = pm_acpi_smi_cmd_port(); struct smmstore_params_init args; uint32_t eax = ~0; uint32_t ebx; @@ -63,7 +64,7 @@ : "=a" (eax) : "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE), "b" (ebx), - "d" (APM_CNT) + "d" (apmc_port) : "memory"); if (eax != SMMSTORE_RET_SUCCESS) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 Gerrit-Change-Number: 79766 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: superio/fintek/f71808a/f71808a_hwm.c: Fix writing to hardware monitor...
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Ravi Mistry. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69260?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: superio/fintek/f71808a/f71808a_hwm.c: Fix writing to hardware monitor registers ...................................................................... Patch Set 3: (1 comment) File src/superio/fintek/f71808a/f71808a_hwm.c: https://review.coreboot.org/c/coreboot/+/69260/comment/4dfc7c80_2740bfc1 : PS3, Line 57: pnp_write_index i'd use pnp_write_hwm5_index in this file instead of adjusting the port, since we already have this specific helper function for this case -- To view, visit https://review.coreboot.org/c/coreboot/+/69260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13e91e9900cfd151d143af4530d18ece2dbbe647 Gerrit-Change-Number: 69260 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi Mistry Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Ravi Mistry Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Ravi Mistry Gerrit-Comment-Date: Sun, 31 Dec 2023 20:01:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Arthur Heymans. Felix Held has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/79677?usp=email ) Change subject: nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled ...................................................................... nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled Don't generate the IVRS ACPI table if the IOMMU PCI device isn't enabled in the devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79677/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a Gerrit-Change-Number: 79677 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: libpayload: Remove shell for loops in install Makefile target
by Felix Singer (Code Review) 31 Dec '23

31 Dec '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79523?usp=email ) Change subject: libpayload: Remove shell for loops in install Makefile target ...................................................................... libpayload: Remove shell for loops in install Makefile target They always require special care so that line breaks and variable names are escaped properly. One loop can be removed entirely because install accepts multiple files to install in a target directories, the other loops were filled by find which can just call the commands on its own. Change-Id: I9f9dddfe3f3ceceb6a0510d6dd862351e4b10210 Signed-off-by: Patrick Georgi <patrick(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79523 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/Makefile.inc 1 file changed, 5 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index c511e128..e4d45a6 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -120,23 +120,16 @@ install: real-target printf " INSTALL $(DESTDIR)/libpayload/lib\n" install -m 755 -d $(DESTDIR)/libpayload/lib - for lib in $(library-targets); do \ - install -m 644 $$lib $(DESTDIR)/libpayload/lib/; \ - done + install -m 644 $(library-targets) $(DESTDIR)/libpayload/lib/ install -m 644 arch/$(ARCHDIR-y)/libpayload.ldscript $(DESTDIR)/libpayload/lib/ install -m 755 -d $(DESTDIR)/libpayload/lib/$(ARCHDIR-y) install -m 644 $(obj)/head.o $(DESTDIR)/libpayload/lib/$(ARCHDIR-y) printf " INSTALL $(DESTDIR)/libpayload/include\n" install -m 755 -d $(DESTDIR)/libpayload/include - for file in `find include -name *.h -type f`; do \ - install -m 755 -d $(DESTDIR)/libpayload/`dirname $$file`; \ - install -m 644 $$file $(DESTDIR)/libpayload/$$file; \ - done - for file in `find $(coreboottop)/src/commonlib/bsd/include -name *.h -type f`; do \ - dest_file=$$(realpath --relative-to=$(coreboottop)/src/commonlib/bsd/ $$file); \ - install -m 755 -d "$(DESTDIR)/libpayload/`dirname $$dest_file`"; \ - install -m 644 "$$file" "$(DESTDIR)/libpayload/$$dest_file"; \ - done + find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \; + find include -type f -exec install -m644 {} $(DESTDIR)/libpayload/{} \; + cd $(coreboottop)/src/commonlib/bsd && find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \; + cd $(coreboottop)/src/commonlib/bsd && find include -type f -exec install -m644 {} $(DESTDIR)/libpayload/{} \; install -m 644 $(obj)/libpayload-config.h $(DESTDIR)/libpayload/include $(foreach item,$(includes), \ install -m 755 -d $(DESTDIR)/libpayload/include/$(call extract_nth,2,$(item)); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/79523?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f9dddfe3f3ceceb6a0510d6dd862351e4b10210 Gerrit-Change-Number: 79523 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: libpayload: Remove shell for loops in install Makefile target
by Felix Singer (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Martin Roth, Patrick Georgi. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79523?usp=email ) Change subject: libpayload: Remove shell for loops in install Makefile target ...................................................................... Patch Set 3: Code-Review+2 (2 comments) File payloads/libpayload/Makefile.inc: https://review.coreboot.org/c/coreboot/+/79523/comment/8ca3443c_56132c5d : PS2, Line 130: find include -type f -exec install -m644 {} $(DESTDIR)/libpayload/{} \; > I think this wasn't done because -D is a GNU extension. Not sure if anybody still cares, though... Done https://review.coreboot.org/c/coreboot/+/79523/comment/2b1a3e9e_ea422f9f : PS2, Line 131: cd $(coreboottop)/src/commonlib/bsd && find include -type d -exec install -m755 -d $(DESTDIR)/libpayload/{} \; : c > same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79523?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f9dddfe3f3ceceb6a0510d6dd862351e4b10210 Gerrit-Change-Number: 79523 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Comment-Date: Sun, 31 Dec 2023 18:45:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Patrick Georgi <patrick(a)coreboot.org> Gerrit-MessageType: comment

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coreboot-gerrit December 2023