coreboot-gerrit December 2023

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[S] Change in coreboot[main]: mb/google/nissa/var/craask: Add ILTK touchscreen
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79735?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/craask: Add ILTK touchscreen ...................................................................... mb/google/nissa/var/craask: Add ILTK touchscreen Add touchscreen ILTK for craaskwell. Refer to ILI2901A-A200 Data Sheet_V1.1_20231026. BUG=b:308873706 TEST=build and check touchscreen function on craask Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79735 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: Tyler Wang: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 9fff00f..afc3519 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -37,6 +37,7 @@ field TS_SOURCE 38 41 option TS_UNPROVISIONED 0 option TS_GTCH7503 1 + option TS_ILTK0001 2 end end @@ -390,6 +391,23 @@ probe TS_SOURCE TS_UNPROVISIONED end end + chip drivers/i2c/hid + register "generic.hid" = ""ILTK0001"" + register "generic.desc" = ""ILITEK Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "200" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "200" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 41 on + probe TS_SOURCE TS_ILTK0001 + end + end end device ref i2c2 on chip drivers/intel/mipi_camera -- To view, visit https://review.coreboot.org/c/coreboot/+/79735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a68855b1659ff0c9cd33a0ec9acbd289f525a3d Gerrit-Change-Number: 79735 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/google/dedede: Create dita variant
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79655?usp=email ) Change subject: mb/google/dedede: Create dita variant ...................................................................... mb/google/dedede: Create dita variant Create the dita variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:317292413 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DITA Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79655 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/dita/Makefile.inc A src/mainboard/google/dedede/variants/dita/gpio.c A src/mainboard/google/dedede/variants/dita/include/variant/ec.h A src/mainboard/google/dedede/variants/dita/include/variant/gpio.h A src/mainboard/google/dedede/variants/dita/memory/Makefile.inc A src/mainboard/google/dedede/variants/dita/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/dita/overridetree.cb A src/mainboard/google/dedede/variants/dita/ramstage.c A src/mainboard/google/dedede/variants/dita/variant.c 12 files changed, 524 insertions(+), 0 deletions(-) Approvals: David Wu: Looks good to me, approved build bot (Jenkins): Verified Derek Huang: Looks good to me, approved Sheng-Liang Pan: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index cfbe32f..3e47e3c 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -235,6 +235,13 @@ select RT8168_SET_LED_MODE select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR +config BOARD_GOOGLE_DITA + select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR + if BOARD_GOOGLE_BASEBOARD_DEDEDE config BASEBOARD_DEDEDE_LAPTOP @@ -308,6 +315,7 @@ default "Taranza" if BOARD_GOOGLE_TARANZA default "Boxy" if BOARD_GOOGLE_BOXY default "Dexi" if BOARD_GOOGLE_DEXI + default "Dita" if BOARD_GOOGLE_DITA config MAX_CPUS int @@ -351,6 +359,7 @@ default "taranza" if BOARD_GOOGLE_TARANZA default "boxy" if BOARD_GOOGLE_BOXY default "dexi" if BOARD_GOOGLE_DEXI + default "dita" if BOARD_GOOGLE_DITA endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 8c00008..52ff27a 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -94,3 +94,6 @@ config BOARD_GOOGLE_DEXI bool "-> Dexi" + +config BOARD_GOOGLE_DITA + bool "-> Dita" diff --git a/src/mainboard/google/dedede/variants/dita/Makefile.inc b/src/mainboard/google/dedede/variants/dita/Makefile.inc new file mode 100644 index 0000000..c4bbd20 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c + +ramstage-y += variant.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/dedede/variants/dita/gpio.c b/src/mainboard/google/dedede/variants/dita/gpio.c new file mode 100644 index 0000000..2998592 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/gpio.c @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + /* A12 : USB_OC1_N */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : USB_OC2_N */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : USB_OC3_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A18 : USB_OC0_N */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* B9 : LAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + + /* D2 : PWM_PP3300_BUZZER */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D4 : LAN_PE_ISOLATE_ODL_R */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* D17 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_D17, 1, PLTRST), + /* D19 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_D19, NONE), + /* D20 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_D20, NONE), + + /* E13 : GPP_E13/DDI0_DDC_SCL */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14 : GPP_E14/DDI0_DDC_SDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : GPP_E15/DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + /* E16 : GPP_E16/DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD_ODL */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + /* G7 : SD_SDIO_WP */ + PAD_NC(GPP_G7, NONE), + + /* H4 : AP_I2C_TS_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : AP_I2C_CAM_SDA */ + PAD_NC(GPP_H6, NONE), + /* H7 : AP_I2C_CAM_SCL */ + PAD_NC(GPP_H7, NONE), + /* H15 : I2S_SPK_BCLK */ + PAD_NC(GPP_H15, NONE), + + /* R6 : I2S_SPK_LRCK */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S_SPK_AUDIO */ + PAD_NC(GPP_R7, NONE), + + /* S2 : DMIC1_CLK */ + PAD_NC(GPP_S2, NONE), + /* S3 : DMIC1_DATA */ + PAD_NC(GPP_S3, NONE), + /* S6 : DMIC0_CLK */ + PAD_NC(GPP_S6, NONE), + /* S7 : DMIC0_DATA */ + PAD_NC(GPP_S7, NONE), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +static const gpio_t hpd_gpios[] = { + /* HDMI1 */ + GPP_A17, + /* HDMI2 */ + GPP_A16, + /* USB C0 */ + GPP_B23, +}; + +const gpio_t *variant_hpd_gpios(size_t *num) +{ + *num = ARRAY_SIZE(hpd_gpios); + return hpd_gpios; +} diff --git a/src/mainboard/google/dedede/variants/dita/include/variant/ec.h b/src/mainboard/google/dedede/variants/dita/include/variant/ec.h new file mode 100644 index 0000000..039e46b --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/dibbi/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/dita/include/variant/gpio.h b/src/mainboard/google/dedede/variants/dita/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/dita/memory/Makefile.inc b/src/mainboard/google/dedede/variants/dita/memory/Makefile.inc new file mode 100644 index 0000000..5175f13 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/memory/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dita/memory/ src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL, H54G56CYRBX247 diff --git a/src/mainboard/google/dedede/variants/dita/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/dita/memory/dram_id.generated.txt new file mode 100644 index 0000000..83ae8c39 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/memory/dram_id.generated.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dita/memory/ src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) +H54G46CYRBX267 0 (0000) +H54G56CYRBX247 1 (0001) diff --git a/src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt new file mode 100644 index 0000000..f6f0da6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/memory/mem_parts_used.txt @@ -0,0 +1,16 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT53E512M32D1NP-046 WT:B +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL +H54G46CYRBX267 +H54G56CYRBX247 diff --git a/src/mainboard/google/dedede/variants/dita/overridetree.cb b/src/mainboard/google/dedede/variants/dita/overridetree.cb new file mode 100644 index 0000000..2b09088 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/overridetree.cb @@ -0,0 +1,304 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[4] = { + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 190, + .scl_hcnt = 100, + .sda_hold = 40, + } + }, + }" + + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + }" + + # Enable Root Port 3 (index 2) for LAN + # External PCIe port 7 is mapped to PCIe Root Port 3 + register "PcieRpEnable[2]" = "1" + register "PcieClkSrcUsage[4]" = "2" + + # Enable Root Port 7 (index 6) for WLAN + # External PCIe port 3 is mapped to PCIe Root Port 7 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + + # Disable PCIe Root Port 8 + register "PcieRpEnable[7]" = "0" + + # Audio related configurations + register "PchHdaAudioLinkDmicEnable[0]" = "0" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + + # Disable SD card + register "sdcard_cd_gpio" = "0" + register "SdCardPowerEnableActiveHigh" = "0" + + # Disable eDP on port A + register "DdiPortAConfig" = "0" + + # Enable HPD and DDC for DDI port A + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "1" + + # Does not support external vnn power rail + register "disable_external_bypass_vr" = "1" + + # USB Port Configuration + register "usb2_ports[0]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC1, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A0 + register "usb2_ports[2]" = "{ + .enable = 1, + .ocpin = OC2, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A1 + register "usb2_ports[3]" = "{ + .enable = 1, + .ocpin = OC3, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A2 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC0, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A3 + register "usb2_ports[6]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_11P25MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-A Port A4 + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3 + + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | + USB_PORT_WAKE_ENABLE(7)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | + USB_PORT_WAKE_ENABLE(2) | + USB_PORT_WAKE_ENABLE(3) | + USB_PORT_WAKE_ENABLE(4) | + USB_PORT_WAKE_ENABLE(5) | + USB_PORT_WAKE_ENABLE(6)" + + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000) + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN) + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 100, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Power"" + register "options.tsr[2].desc" = ""Chassis"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 on end + end + end # SA Thermal device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 3)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A4"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A4"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 3)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A3"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device usb 3.5 on end + end + end + end + end # USB xHCI + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C 4 + device pci 1c.2 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW0_03" # GPP_B3 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + register "device_index" = "0" + device pci 00.0 on end + end + end # PCI Express Root Port 3 - RTL8111H LAN + device pci 1c.6 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 7 - WLAN + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1f.3 on end # Intel HDA + end +end diff --git a/src/mainboard/google/dedede/variants/dita/ramstage.c b/src/mainboard/google/dedede/variants/dita/ramstage.c new file mode 100644 index 0000000..9bce5e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/ramstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +/* + * Psys_pmax considerations + * + * Given the hardware design in dexi, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638) + * R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000, + .bj_power_w = 65, +}; + +void variant_devtree_update(void) +{ + variant_update_psys_power_limits(&psys_config); +} diff --git a/src/mainboard/google/dedede/variants/dita/variant.c b/src/mainboard/google/dedede/variants/dita/variant.c new file mode 100644 index 0000000..8be5396 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dita/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar-dexi.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Gerrit-Change-Number: 79655 Gerrit-PatchSet: 4 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/google/dedede: Create dita variant
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Lucas Chen, Sheng-Liang Pan. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79655?usp=email ) Change subject: mb/google/dedede: Create dita variant ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/dedede/variants/dita/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79655/comment/169b5f52_489f0023 : PS3, Line 122: # the indentation is different here compared to the two lines below. might be good to make this match the other comments or the other two comments match this one. -- To view, visit https://review.coreboot.org/c/coreboot/+/79655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e33f30cd356e4f12330bdfe2d53a0b3920ef3 Gerrit-Change-Number: 79655 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Sun, 31 Dec 2023 18:09:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Krystian Hebel, Michał Żygowski, Nico Huber, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79612?usp=email ) Change subject: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration ...................................................................... Patch Set 7: (1 comment) File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/c/coreboot/+/79612/comment/06755445_431888d9 : PS2, Line 277: val = pci_read_config32(DEV_PTR(ht_3), 0xB8); : val &= 0xF000003F; : pci_write_config32(DEV_PTR(ht_3), 0xB8, val); > if my understanding is correctly, bit 26 and 27 need to be 0 for ecc error injection to work; still […] since clearing all reserved bits from 10..27 should be safe to do and the public documentation is missing part of the register description, i'd say that we should just clear all those reserved bits. still leaving the other unresolved comment unresolved, since it might be better to test again before submitting this change -- To view, visit https://review.coreboot.org/c/coreboot/+/79612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb0cb117bedf900642e93c556a64800e1e52b6ea Gerrit-Change-Number: 79612 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sun, 31 Dec 2023 18:03:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79677?usp=email ) Change subject: nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled ...................................................................... Patch Set 2: (1 comment) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/79677/comment/e5b47677_31517524 : PS1, Line 442: is_devfn_enabled > is_dev_enabled good catch; fixed -- To view, visit https://review.coreboot.org/c/coreboot/+/79677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a Gerrit-Change-Number: 79677 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 31 Dec 2023 17:57:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled
by Felix Held (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Felix Held. Felix Held has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79677?usp=email ) Change subject: nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled ...................................................................... nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled Don't generate the IVRS ACPI table if the IOMMU PCI device isn't enabled in the devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79677/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a Gerrit-Change-Number: 79677 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: security/intel/txt: Add support for x86_64
by Patrick Rudolph (Code Review) 31 Dec '23

31 Dec '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79757?usp=email ) Change subject: security/intel/txt: Add support for x86_64 ...................................................................... security/intel/txt: Add support for x86_64 Add support for x86_64 by using protected_mode wrapper functions. UNTESTED. Change-Id: I9ff12d1cc85931e5a68866223d346bfea9ca7c30 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/intel/txt/common.c M src/security/intel/txt/getsec_enteraccs.S M src/security/intel/txt/getsec_sclean.S 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/79757/1 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index b78394a..8d1b9be 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -8,6 +8,7 @@ #include <cpu/x86/mtrr.h> #include <device/mmio.h> #include <lib.h> +#include <mode_switch.h> #include <smp/node.h> #include <string.h> #include <types.h> @@ -335,7 +336,7 @@ /* * Invoke the BIOS ACM. If successful, the system will reset with memory unlocked. */ - getsec_sclean((uintptr_t)acm_data, acm_len); + protected_mode_call_2arg(getsec_sclean, (uintptr_t)acm_data, acm_len); /* * However, if this function returns, the BIOS ACM could not be invoked. This is bad. @@ -360,7 +361,8 @@ return -1; /* Call into assembly which invokes the referenced ACM */ - getsec_enteraccs(input_params, (uintptr_t)acm_data, acm_len); + protected_mode_call_3arg(getsec_enteraccs, input_params, + (uintptr_t)acm_data, acm_len); cbfs_unmap(acm_data); diff --git a/src/security/intel/txt/getsec_enteraccs.S b/src/security/intel/txt/getsec_enteraccs.S index ff9db05..a6f21b2 100644 --- a/src/security/intel/txt/getsec_enteraccs.S +++ b/src/security/intel/txt/getsec_enteraccs.S @@ -30,6 +30,7 @@ .align 4 .text +.code32 /* * See "SAFER MODE EXTENSIONS REFERENCE." diff --git a/src/security/intel/txt/getsec_sclean.S b/src/security/intel/txt/getsec_sclean.S index 0944e15..6a5b105 100644 --- a/src/security/intel/txt/getsec_sclean.S +++ b/src/security/intel/txt/getsec_sclean.S @@ -10,6 +10,7 @@ .align 4 .text +.code32 /* * void getsec_sclean(const uint32_t acm_base, const uint32_t acm_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/79757?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ff12d1cc85931e5a68866223d346bfea9ca7c30 Gerrit-Change-Number: 79757 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: arch/x86/include/mode_switch: Add more wrapper functions
by Patrick Rudolph (Code Review) 31 Dec '23

31 Dec '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79756?usp=email ) Change subject: arch/x86/include/mode_switch: Add more wrapper functions ...................................................................... arch/x86/include/mode_switch: Add more wrapper functions Add a protected mode wrapper function that takes three arguments. This is already supported by the called assembly code. Change-Id: Ia8c91eebae17e4ca27e391454c2d130a71c4c9f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/mode_switch.h M src/cpu/x86/64bit/mode_switch.S 2 files changed, 31 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/79756/1 diff --git a/src/arch/x86/include/mode_switch.h b/src/arch/x86/include/mode_switch.h index 4235db9..54969b2 100644 --- a/src/arch/x86/include/mode_switch.h +++ b/src/arch/x86/include/mode_switch.h @@ -11,10 +11,10 @@ * * The called function has 0-3 arguments and returns an int. */ -int protected_mode_call_3arg(uint32_t func_ptr, - uint32_t opt_arg1, - uint32_t opt_arg2, - uint32_t opt_arg3); +int protected_mode_call_wrapper(uint32_t func_ptr, + uint32_t opt_arg1, + uint32_t opt_arg2, + uint32_t opt_arg3); /* * Drops into protected mode and calls the function, which must have been compiled for x86_32. @@ -25,7 +25,7 @@ */ static inline int protected_mode_call(void *func) { - return protected_mode_call_3arg((uintptr_t)func, 0, 0, 0); + return protected_mode_call_wrapper((uintptr_t)func, 0, 0, 0); } /* @@ -38,7 +38,7 @@ */ static inline int protected_mode_call_1arg(void *func, uint32_t arg1) { - return protected_mode_call_3arg((uintptr_t)func, arg1, 0, 0); + return protected_mode_call_wrapper((uintptr_t)func, arg1, 0, 0); } /* @@ -51,7 +51,21 @@ */ static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2) { - return protected_mode_call_3arg((uintptr_t)func, arg1, arg2, 0); + return protected_mode_call_wrapper((uintptr_t)func, arg1, arg2, 0); +} + +/* + * Drops into protected mode and calls the function, which must have been compiled for x86_32. + * After the function returns it enters long mode again. + * The function pointer destination must be below 4GiB in physical memory. + * Only the lower 32bits of the argument are passed to the called function. + * + * The called function has two arguments and returns an int. + */ +static inline int protected_mode_call_3arg(void *func, uint32_t arg1, uint32_t arg2, + uint32_t arg3) +{ + return protected_mode_call_wrapper((uintptr_t)func, arg1, arg2, arg3); } #else static inline int protected_mode_call(void *func) @@ -74,4 +88,12 @@ return doit(arg1, arg2); } + +static inline int protected_mode_call_3arg(void *func, uint32_t arg1, uint32_t arg2, + uint32_t arg3) +{ + int (*doit)(uint32_t arg1, uint32_t arg2, uint32_t arg3) = func; + + return doit(arg1, arg2, arg3); +} #endif diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index f9f784e..c4198f3 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -4,8 +4,8 @@ .text .code64 .section ".text.protected_mode_call", "ax", @progbits - .globl protected_mode_call_3arg -protected_mode_call_3arg: + .globl protected_mode_call_wrapper +protected_mode_call_wrapper: /* Preserve registers */ push %rbp push %rbx -- To view, visit https://review.coreboot.org/c/coreboot/+/79756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8c91eebae17e4ca27e391454c2d130a71c4c9f3 Gerrit-Change-Number: 79756 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: cpu/x86/64bit/mode_switch2: The reverse function to mode_switch
by Patrick Rudolph (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Jérémy Compostella, Patrick Rudolph. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79753?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: cpu/x86/64bit/mode_switch2: The reverse function to mode_switch ...................................................................... cpu/x86/64bit/mode_switch2: The reverse function to mode_switch Add another mode_switch assembly function to call x86_64 code from x86_32 code. This is particullary useful for BLOBs like mrc.bin or FSP that calls back into coreboot. The user must first wrap all functions that are to be called from x86_32 using the macro prot2lm_wrapper. Instead of using the original function the wrapped functions must be passed to the x86_32 BLOBs. The assembly code assume that 0-3 32bit arguments are passed to the wrapped function. Tested: - Called x86_64 code from x86_32 code in qemu. - Booted Lenovo X220 using x86_32 MRC using x86_64 console. Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/Makefile.inc A src/cpu/x86/64bit/mode_switch2.S A src/cpu/x86/64bit/prot2long.inc 3 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/79753/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79753?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib625233e5f673eae9f3dcb2d03004c06bb07b149 Gerrit-Change-Number: 79753 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: northbridge/intel/sandybridge: Enable x86_64 for mrc.bin
by Patrick Rudolph (Code Review) 31 Dec '23

31 Dec '23

Attention is currently required from: Angel Pons, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79754?usp=email ) Change subject: northbridge/intel/sandybridge: Enable x86_64 for mrc.bin ...................................................................... Patch Set 3: (1 comment) File src/northbridge/intel/sandybridge/mrc_wrapper.S: https://review.coreboot.org/c/coreboot/+/79754/comment/25507dfd_a787932f : PS2, Line 37: mrc_console_wrapper: : /* Set up new stack frame */ : pushal : mov %esp, %ebp : : /* Align stack and make space for arguments */ : andl $0xfffffff0, %esp : subl $8, %esp : : /* Get argument */ : movl 36(%ebp), %eax : push %eax : : /* Get function to call */ : mov $do_putchar, %eax : push %eax : : /* : * Elevate to long mode. As 2nd and 3rd argument are unused they : * haven't been pushed to the stack. : */ : call long_mode_call_3arg : : /* Restore stack pointer */ : mov %ebp, %esp : popal > FSP also has callbacks into coreboot. […] Replaced with a macro. -- To view, visit https://review.coreboot.org/c/coreboot/+/79754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21ffcb5f5d4bf155593e8111531bdf0ed7071dfc Gerrit-Change-Number: 79754 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 31 Dec 2023 11:21:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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