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Change subject: soc/intel/braswell: Unify DPTF enablement
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/cyan/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/78743/comment/089d4e34_9068a413 :
PS2, Line 98: off
> strago is currently set to on / I didn't change it, just corrected the comment to make it consistent with other BSW boards.
Right. my bad.
>
> cyan I had previously intentionally disabled, but missed that it was being overridden by the FSP UPD, so I was setting the intended behavior. If you'd prefer I set it on here and disable in a follow-on patch to make that more clear, I'm happy to do so
If it's intentional, then it's fine. Just mention it in the commit message, please,
maybe reference the commit for the reason.
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Change subject: soc/intel/braswell: Unify DPTF enablement
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/cyan/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/78743/comment/89a8fc69_4e7e5711 :
PS2, Line 98: off
> I would assume that `DptfDisable` had the strongest meaning (i.e. the blob […]
strago is currently set to on / I didn't change it, just corrected the comment to make it consistent with other BSW boards.
cyan I had previously intentionally disabled, but missed that it was being overridden by the FSP UPD, so I was setting the intended behavior. If you'd prefer I set it on here and disable in a follow-on patch to make that more clear, I'm happy to do so
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Hello Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78823?usp=email
to look at the new patch set (#4).
Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly
......................................................................
soc/amd/*: Ensure PSP soft fuse bitmask set properly
Commit e728766f4596 ("soc/amd/mendocino: Do not load MP2 Firmware when
in RO") added logic to ensure that the MP2 disable soft fuse bit was set
for the RO section, but failed to check if the bit was already set
otherwise (as it is for non-ChromeOS builds). This caused the bit to
appear twice in the PSP_RO_SOFTFUSE_BITS string, and when the string
was converted to a series of numeric values and added together, bit
(n+1) ended up being set instead of bit n.
To mitigate this, use the makefile sort() function to ensure the
PSP_[RO_]SOFTFUSE_BITS string does not contain and duplicates before
the bitmask is calculated. Apply this to all AMD SoC makefiles where
the softfuse bits are added.
TEST=build/boot google/skyrim (frostflow). Use a verbose build (V=1)
to verify that the correct soft fuse value is passed to amdfwtool for
RO and RW_A/B for both ChromeOS and non-ChromeOS builds.
Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5
Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/genoa/Makefile.inc
M src/soc/amd/glinda/Makefile.inc
M src/soc/amd/mendocino/Makefile.inc
M src/soc/amd/phoenix/Makefile.inc
M src/soc/amd/picasso/Makefile.inc
6 files changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/78823/4
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Change subject: SNB+MRC boards: Migrate MRC settings to devicetree
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS5:
> @Nico Does the Roda Lizard RW11 use the PEG10 slot?
There's an optional MXM connector. However not on our models and hence untested.
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Change subject: payloads/LinuxBoot: Hide the path of the kernel and initrd when building
......................................................................
Patch Set 1: Code-Review+1
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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74798/comment/4eac0578_89a37ba7 :
PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards.
> Okay, so I have resolved all comments. […]
Just to make sure we're on the same page: We actually think it's wrong. We do it
anyway because $vendor. Chances to rectify things after the platform is upstream
are close to 0 because discussions with $vendor about it haven't even started yet.
Is that correct?
And to have it said: arguments that discussions will be too slow / too late
usually don't help when somebody forgot to start them a year ago.
If Julius agrees to the patch, I won't object. However, I would wait with merging
until there was an actual decision to accept Ampere support upstream (we don't
know yet what other obstacles exist and what other people think of a shimboot).
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Documentation: add Nitrokey to distributions
Nitrokey offers various products, which have coreboot pre-installed.
Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a
Signed-off-by: Markus Meissner <coder(a)safemailbox.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78299
Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M Documentation/distributions.md
1 file changed, 10 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
diff --git a/Documentation/distributions.md b/Documentation/distributions.md
index 139e5b6..219c659 100644
--- a/Documentation/distributions.md
+++ b/Documentation/distributions.md
@@ -8,6 +8,16 @@
## Hardware shipping with coreboot
+### Nitrokey
+
+[Nitrokey](https://nitrokey.com) is a german IT security hardware vendor which
+offers a range of laptops, PCs, HSMs, and networking devices with coreboot and
+[Dasharo](https://dasharo.com/). The devices come with neutralized Intel
+Management Engine (ME) and with pre-installed [Heads](http://osresearch.net) or
+EDK2 payload providing measured boot and verified boot protection. For
+additional security the systems can be physically sealed and pictures of those
+sealings are sent via encrypted email.
+
### NovaCustom laptops
[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/braswell: Unify DPTF enablement
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Patchset:
PS2:
Thanks for cleaning this up!
File src/mainboard/google/cyan/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/78743/comment/f4799e13_51d05a0f :
PS2, Line 98: off
I would assume that `DptfDisable` had the strongest meaning (i.e. the blob
actually disables the device, while `off` only made coreboot ignore it).
As it wasn't set, shouldn't we turn the device `on` here?
Same for Strago.
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Change subject: soc/intel/braswell/Kconfig: Set HPET_MIN_TICKS
......................................................................
Patch Set 4: Code-Review+1
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