coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: mb/google/hatch: Change WiFi device type from PCI to generic
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro, Subrata Banik. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78543?usp=email ) Change subject: mb/google/hatch: Change WiFi device type from PCI to generic ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I just want to note that we discussed the pros & cons of this change. It *is* a pci device, but it's using a bogus device/func, which says that it doesn't actually need any of the PCI information. Because the device is already inside a generic driver, it seems entirely appropriate to continue with it as a generic. -- To view, visit https://review.coreboot.org/c/coreboot/+/78543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418 Gerrit-Change-Number: 78543 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Nov 2023 15:37:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust Power State Current 2 threshold
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78653?usp=email ) Change subject: soc/intel/meteorlake: Adjust Power State Current 2 threshold ...................................................................... soc/intel/meteorlake: Adjust Power State Current 2 threshold VccSA Power State 2 (PS2) current threshold has be adjusted to 10A to improve PS2 residency which reduces Voltage Regular (VR) power loss. BUG=b:308002192 TEST=power and performance analysis shows a positive Load Line result Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/romstage/fsp_params.c 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Sukumar Ghorai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index e860ba97..59b6a8b 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -306,6 +306,30 @@ */ uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS]; + /* + * Power state current threshold 1. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_1_threshold[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 2. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_2_threshold[NUM_VR_DOMAINS]; + + /* + * Power state current threshold 3. + * Defined in 1/4 A increments. A value of 400 = 100A. Range 0-512, + * which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for + * SA, [3] through [5] are Reserved. + */ + uint16_t ps_cur_3_threshold[NUM_VR_DOMAINS]; + uint8_t PmTimerDisabled; /* * SerialIO device mode selection: diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 69d0df3..865b3d0 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -17,6 +17,10 @@ # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true" + # The power state current threshold is defined in 1/4 A + # increments. A value of 400 = 100A. + register "ps_cur_2_threshold[VR_DOMAIN_SA]" = "40" # 10A + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 8f64d4f..2c39bcd 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -238,6 +238,12 @@ m_cfg->IccLimit[domain] = config->fast_vmode_i_trip[domain]; } } + if (config->ps_cur_1_threshold[domain]) + m_cfg->Psi1Threshold[domain] = config->ps_cur_1_threshold[domain]; + if (config->ps_cur_2_threshold[domain]) + m_cfg->Psi2Threshold[domain] = config->ps_cur_2_threshold[domain]; + if (config->ps_cur_3_threshold[domain]) + m_cfg->Psi3Threshold[domain] = config->ps_cur_3_threshold[domain]; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/78653?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2da2b05de8a04f91dacaa55062165c4351422865 Gerrit-Change-Number: 78653 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: drivers/generic/adau7002: Set ACPI status to hidden
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78510?usp=email ) Change subject: drivers/generic/adau7002: Set ACPI status to hidden ...................................................................... drivers/generic/adau7002: Set ACPI status to hidden No driver available or needed under Windows, so hide from OS. TEST=build/boot Win11 on google/kahlee (liara), verify ADAU7002 device no longer listed as unknown under Device Manager. Boot Linux and verify audio still functional. Change-Id: If6d250a123825a69441b5c4d3cde35d5a68f568d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78510 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/generic/adau7002/adau7002.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 26da09b..63510cd 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -31,7 +31,7 @@ acpigen_write_name_string("_HID", ADAU7002_ACPI_HID); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); - acpigen_write_STA(acpi_device_status(dev)); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* _DSD for devicetree properties */ config = dev->chip_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/78510?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6d250a123825a69441b5c4d3cde35d5a68f568d Gerrit-Change-Number: 78510 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brya/var/omnigul: Add fingerprint SPI
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Jamie Chen, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun Tuli. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78427?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brya/var/omnigul: Add fingerprint SPI ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/brya/variants/omnigul/overridetree.cb: https://review.coreboot.org/c/coreboot/+/78427/comment/046f330e_ea7349ff : PS9, Line 337: n mind changing this to hidden to be consistent with the change made to other brya boards? -- To view, visit https://review.coreboot.org/c/coreboot/+/78427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Gerrit-Change-Number: 78427 Gerrit-PatchSet: 9 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Nov 2023 15:35:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/{google,intel}: Update FMD to support CBFS verification
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78502?usp=email ) Change subject: mb/{google,intel}: Update FMD to support CBFS verification ...................................................................... mb/{google,intel}: Update FMD to support CBFS verification This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed for boards that currently use them. BUG=b:284382452 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78502 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/brox/chromeos.fmd M src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd M src/mainboard/google/brya/chromeos-nissa-16MiB.fmd M src/mainboard/google/brya/chromeos-nissa-32MiB.fmd M src/mainboard/google/brya/chromeos-serger.fmd M src/mainboard/google/brya/chromeos.fmd M src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd M src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd M src/mainboard/google/volteer/chromeos.fmd M src/mainboard/intel/adlrvp/chromeos.fmd M src/mainboard/intel/jasperlake_rvp/chromeos.fmd M src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd M src/mainboard/intel/mtlrvp/chromeos.fmd 13 files changed, 12 insertions(+), 38 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/brox/chromeos.fmd b/src/mainboard/google/brox/chromeos.fmd index 59b24dd..65ceba7 100644 --- a/src/mainboard/google/brox/chromeos.fmd +++ b/src/mainboard/google/brox/chromeos.fmd @@ -14,7 +14,6 @@ VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K } RW_LEGACY(CBFS) 2M RW_MISC 1M { @@ -43,7 +42,6 @@ VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd b/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd index ee92f2a..205f3dd 100644 --- a/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd +++ b/src/mainboard/google/brya/chromeos-nissa-16MiB-debugfsp.fmd @@ -8,7 +8,6 @@ VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 1434K } RW_MISC 152K { UNIFIED_MRC_CACHE(PRESERVE) 128K { @@ -26,7 +25,6 @@ VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 1434K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd index af69207..037812a 100644 --- a/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd +++ b/src/mainboard/google/brya/chromeos-nissa-16MiB.fmd @@ -8,7 +8,6 @@ VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 1434K } RW_LEGACY(CBFS) 1M RW_MISC 152K { @@ -27,7 +26,6 @@ VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 1434K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd index 1662600..00e7997 100644 --- a/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd +++ b/src/mainboard/google/brya/chromeos-nissa-32MiB.fmd @@ -8,7 +8,6 @@ VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 1434K } RW_LEGACY(CBFS) 1M RW_MISC 152K { @@ -33,7 +32,6 @@ VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 1434K } # RW UNUSED Region 2. RW_UNUSED_2 7912K diff --git a/src/mainboard/google/brya/chromeos-serger.fmd b/src/mainboard/google/brya/chromeos-serger.fmd index 72c6429..7284936 100644 --- a/src/mainboard/google/brya/chromeos-serger.fmd +++ b/src/mainboard/google/brya/chromeos-serger.fmd @@ -14,7 +14,6 @@ VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K } RW_LEGACY(CBFS) 2M RW_MISC 1M { @@ -43,7 +42,6 @@ VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd index e445383..ac7e51e 100644 --- a/src/mainboard/google/brya/chromeos.fmd +++ b/src/mainboard/google/brya/chromeos.fmd @@ -14,7 +14,6 @@ VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3008K } RW_LEGACY(CBFS) 2M RW_MISC 1M { @@ -43,7 +42,6 @@ VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3008K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd index ade4866..0e21c4c 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd @@ -7,15 +7,13 @@ RW_LEGACY(CBFS)@0x0 0x100000 RW_SECTION_A@0x100000 0x3a4800 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x2127c0 - RW_FWID_A@0x2147c0 0x40 - ME_RW_A(CBFS)@0x214800 0x190000 + FW_MAIN_A(CBFS)@0x2000 0x3a27c0 + RW_FWID_A@0x3a47c0 0x40 } RW_SECTION_B@0x4a4800 0x3a4800 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x2127c0 - RW_FWID_B@0x2147c0 0x40 - ME_RW_B(CBFS)@0x214800 0x190000 + FW_MAIN_B(CBFS)@0x2000 0x3a27c0 + RW_FWID_B@0x3a47c0 0x40 } RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd index 4b31861..60ea3de 100644 --- a/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd +++ b/src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd @@ -10,15 +10,13 @@ RW_LEGACY(CBFS)@0x0 0xf00000 RW_SECTION_A@0xf00000 0x3e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x23ffc0 - RW_FWID_A@0x24ffc0 0x40 - ME_RW_A(CBFS)@0x250000 0x190000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 } RW_SECTION_B@0x12e0000 0x3e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x23ffc0 - RW_FWID_B@0x24ffc0 0x40 - ME_RW_B(CBFS)@0x250000 0x190000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 6f833fe..1e3e77b 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -8,7 +8,6 @@ VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3M } RW_LEGACY(CBFS) 2M RW_MISC 1M { @@ -32,7 +31,6 @@ VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3M } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd index 53469de..0e8d321 100644 --- a/src/mainboard/intel/adlrvp/chromeos.fmd +++ b/src/mainboard/intel/adlrvp/chromeos.fmd @@ -15,7 +15,6 @@ VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 3520K } RW_LEGACY(CBFS) 1M RW_MISC 1M { @@ -39,7 +38,6 @@ VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 3520K } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index e4e0b24..4fe11de 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -8,15 +8,13 @@ RW_LEGACY(CBFS)@0x0 0x100000 RW_SECTION_A@0x100000 0x3a4800 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x2127c0 - RW_FWID_A@0x2147c0 0x40 - ME_RW_A(CBFS)@0x214800 0x190000 + FW_MAIN_A(CBFS)@0x2000 0x3a27c0 + RW_FWID_A@0x3a47c0 0x40 } RW_SECTION_B@0x4a4800 0x3a4800 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x2127c0 - RW_FWID_B@0x2147c0 0x40 - ME_RW_B(CBFS)@0x214800 0x190000 + FW_MAIN_B(CBFS)@0x2000 0x3a27c0 + RW_FWID_B@0x3a47c0 0x40 } RW_MISC@0x849000 0x36000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { diff --git a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd index 6ca1cc6..d085640 100644 --- a/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos-debug-fsp.fmd @@ -8,7 +8,6 @@ VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 4400K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, @@ -18,7 +17,6 @@ VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 4400K } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd index a5bc538..c32a9f0 100644 --- a/src/mainboard/intel/mtlrvp/chromeos.fmd +++ b/src/mainboard/intel/mtlrvp/chromeos.fmd @@ -8,7 +8,6 @@ VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 - ME_RW_A(CBFS) 4400K } # This section starts at the 16M boundary in SPI flash. # MTL does not support a region crossing this boundary, @@ -18,7 +17,6 @@ VBLOCK_B 8K FW_MAIN_B(CBFS) RW_FWID_B 64 - ME_RW_B(CBFS) 4400K } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { -- To view, visit https://review.coreboot.org/c/coreboot/+/78502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Gerrit-Change-Number: 78502 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/{google,intel}: Update FMD to support CBFS verification
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Anil Kumar K, Eric Lai, Jérémy Compostella, Nick Vaccaro, Subrata Banik. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78502?usp=email ) Change subject: mb/{google,intel}: Update FMD to support CBFS verification ...................................................................... Patch Set 3: (3 comments) File src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd: https://review.coreboot.org/c/coreboot/+/78502/comment/6c753111_2fc227b4 : PS3, Line 10: 0x3a27c0 > Just remove the length (both here and below) so that FW_MAIN_A/B takes up all the remaining space? […] Oh, after reading Julius' comments, I guess it's one or the other. I agree with Julius that just removing the offsets would be better, but I guess that could be done across all platforms in a future commit. File src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd: https://review.coreboot.org/c/coreboot/+/78502/comment/e17b3e19_997a0757 : PS3, Line 13: 0x3cffc0 > Same, just remove the lengths. Done File src/mainboard/intel/jasperlake_rvp/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/78502/comment/a4c05297_161fe240 : PS3, Line 11: @0x2000 0x3a27c0 > You get the idea. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Gerrit-Change-Number: 78502 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Nov 2023 15:33:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78824?usp=email ) Change subject: mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI ...................................................................... mb/google/geralt: Enable FW_CONFIG and FW_CONFIG_SOURCE_CHROMEEC_CBI Enable FW_CONFIG for geralt so that the information can be passed to payloads via coreboot tables. BUG=b:157692450 TEST=emerge-geralt coreboot BRANCH=none Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78824 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/geralt/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index 54c51d8..6817143 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -35,6 +35,8 @@ select HAVE_LINEAR_FRAMEBUFFER select RTC select MIPI_PANEL_BOE_TV110C9M_LL0 if BOARD_GOOGLE_GERALT + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/78824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8898143f44d2ffda3cb1708c2d7efadc289303a1 Gerrit-Change-Number: 78824 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/{google,intel}: Update FMD to support CBFS verification
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Anil Kumar K, Eric Lai, Jérémy Compostella, Nick Vaccaro, Subrata Banik. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78502?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/{google,intel}: Update FMD to support CBFS verification ...................................................................... Patch Set 3: (3 comments) File src/mainboard/google/dedede/chromeos-dedede-16MiB.fmd: https://review.coreboot.org/c/coreboot/+/78502/comment/b242f810_4cc10e0c : PS3, Line 10: 0x3a27c0 Just remove the length (both here and below) so that FW_MAIN_A/B takes up all the remaining space? The locations can also be removed if you want. The FMD tool knows where to put things now based on the previous sizes and locations. File src/mainboard/google/dedede/chromeos-dedede-32MiB.fmd: https://review.coreboot.org/c/coreboot/+/78502/comment/1f038f75_d3fea341 : PS3, Line 13: 0x3cffc0 Same, just remove the lengths. File src/mainboard/intel/jasperlake_rvp/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/78502/comment/49fdf67c_57a1db81 : PS3, Line 11: @0x2000 0x3a27c0 You get the idea. -- To view, visit https://review.coreboot.org/c/coreboot/+/78502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca88fee181f059852923d50292b24c0e5b9fd6d Gerrit-Change-Number: 78502 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Nov 2023 15:32:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/lint: Fix some mistakes in spelling.txt
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78822?usp=email ) Change subject: util/lint: Fix some mistakes in spelling.txt ...................................................................... util/lint: Fix some mistakes in spelling.txt Somehow two words slipped in here where the "bad" and "good" spellings are the same, which doesn't make sense. Remove them. Change-Id: I9b53ce8538616c164efb4eb25ff859975ddadfd2 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78822 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/lint/spelling.txt 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: Felix Singer: Looks good to me, approved Martin L Roth: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 8f515d8..25605ef 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -4136,7 +4136,6 @@ frontent||frontend frops||drops frop||drop -ftbs||ftbs fualts||faults fualt||fault fucntions||functions @@ -7362,7 +7361,6 @@ readabilty||readability readapted||re-adapted readiable||readable -readme||readme realeased||released realeases||releases realease||release -- To view, visit https://review.coreboot.org/c/coreboot/+/78822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b53ce8538616c164efb4eb25ff859975ddadfd2 Gerrit-Change-Number: 78822 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: util/lint: Fix some mistakes in spelling.txt
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Julius Werner. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78822?usp=email ) Change subject: util/lint: Fix some mistakes in spelling.txt ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b53ce8538616c164efb4eb25ff859975ddadfd2 Gerrit-Change-Number: 78822 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Nov 2023 15:26:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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