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Change subject: Documentation: order distributions alphabetically
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/78864/comment/6450d9c9_8e692f62 :
PS1, Line 67: ## After-market firmware
While on it, please reorder these as well
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Change subject: Documentation: order distributions alphabetically
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
As hinted in this change: https://review.coreboot.org/c/coreboot/+/78299
This is the changeset to reorder distributions alphabetically
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Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78823/comment/56a68783_47472038 :
PS4, Line 18: and
> Nit: any
Done
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Hello Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78823?usp=email
to look at the new patch set (#5).
Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly
......................................................................
soc/amd/*: Ensure PSP soft fuse bitmask set properly
Commit e728766f4596 ("soc/amd/mendocino: Do not load MP2 Firmware when
in RO") added logic to ensure that the MP2 disable soft fuse bit was set
for the RO section, but failed to check if the bit was already set
otherwise (as it is for non-ChromeOS builds). This caused the bit to
appear twice in the PSP_RO_SOFTFUSE_BITS string, and when the string
was converted to a series of numeric values and added together, bit
(n+1) ended up being set instead of bit n.
To mitigate this, use the makefile sort() function to ensure the
PSP_[RO_]SOFTFUSE_BITS string does not contain any duplicates before
the bitmask is calculated. Apply this to all AMD SoC makefiles where
the softfuse bits are added.
TEST=build/boot google/skyrim (frostflow). Use a verbose build (V=1)
to verify that the correct soft fuse value is passed to amdfwtool for
RO and RW_A/B for both ChromeOS and non-ChromeOS builds.
Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5
Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/genoa/Makefile.inc
M src/soc/amd/glinda/Makefile.inc
M src/soc/amd/mendocino/Makefile.inc
M src/soc/amd/phoenix/Makefile.inc
M src/soc/amd/picasso/Makefile.inc
6 files changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/78823/5
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Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78823/comment/41075671_b60860be :
PS4, Line 18: and
Nit: any
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Change subject: Documentation: order distributions alphabetically
......................................................................
Documentation: order distributions alphabetically
Change-Id: I95d4347791988087d90992b45120ff34ba2da1c5
Signed-off-by: Markus Meissner <coder(a)safemailbox.de>
---
M Documentation/distributions.md
1 file changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/78864/1
diff --git a/Documentation/distributions.md b/Documentation/distributions.md
index 219c659..3185e0b 100644
--- a/Documentation/distributions.md
+++ b/Documentation/distributions.md
@@ -8,6 +8,15 @@
## Hardware shipping with coreboot
+### ChromeOS Devices
+
+All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
+Chromebit, etc) released from 2012 onward use coreboot for their main system
+firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
+running on the Embedded Controller (EC) – a small microcontroller which provides
+functions like battery management, keyboard support, and sensor interfacing –
+is open source as well.
+
### Nitrokey
[Nitrokey](https://nitrokey.com) is a german IT security hardware vendor which
@@ -27,15 +36,6 @@
and the firmware is equipped with important security features such as measured
boot, verified boot, TPM integration and UEFI Secure Boot.
-### ChromeOS Devices
-
-All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
-Chromebit, etc) released from 2012 onward use coreboot for their main system
-firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
-running on the Embedded Controller (EC) – a small microcontroller which provides
-functions like battery management, keyboard support, and sensor interfacing –
-is open source as well.
-
### PC Engines APUs
[PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that
@@ -43,6 +43,13 @@
third party, [3mdeb](https://3mdeb.com). They provide current and tested
firmware binaries on [GitHub](https://pcengines.github.io).
+### Purism
+
+[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
+security; part of that effort is to minimize the amount of proprietary and/or
+binary code. Their laptops ship with a blob-free OS and coreboot firmware
+with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
+
### Star Labs
[Star Labs](https://starlabs.systems/) offers a range of laptops designed and
@@ -57,13 +64,6 @@
Firmware](https://github.com/system76/firmware-open), an open source
distribution of coreboot, edk2, and System76 firmware applications.
-### Purism
-
-[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
-security; part of that effort is to minimize the amount of proprietary and/or
-binary code. Their laptops ship with a blob-free OS and coreboot firmware
-with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
-
## After-market firmware
### Libreboot
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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 6:
(1 comment)
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/74798/comment/7316fa51_94058ae8 :
PS6, Line 30: 1 (EL1), 2 (EL2) and 3 (EL3)
Nit: Could you maybe define what these are or add why one would be chosen over another?
You can also add "If you don't know what this does, leave at the default." if you wanted.
If you don't think this is needed, feel free to Ack and close.
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Change subject: payloads/LinuxBoot: Hide the path of the kernel and initrd when building
......................................................................
Patch Set 1: Code-Review+2
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78543?usp=email )
Change subject: mb/google/hatch: Change WiFi device type from PCI to generic
......................................................................
mb/google/hatch: Change WiFi device type from PCI to generic
Change the WiFi device type to generic, so that the LPI constraint
generator does not create a reference for a device which does not
exist in ACPI (SB.PCI0.RP14.MCHC). The invalid reference causes
a Windows BSOD.
TEST=build/boot Win11 on google/hatch (akemi)
Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78543
Reviewed-by: Martin L Roth <gaumless(a)gmail.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin L Roth: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 22bb8b7..c4679e3 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -291,7 +291,7 @@
device ref pcie_rp14 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_01"
- device pci 00.0 on end
+ device generic 0 on end
end
register "PcieRpSlotImplemented[13]" = "1"
end # (x1 WiFi)
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