coreboot-gerrit November 2023

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[S] Change in coreboot[main]: Documentation: order distributions alphabetically
by Markus Meissner (Code Review) 01 Nov '23

01 Nov '23

Markus Meissner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78871?usp=email ) Change subject: Documentation: order distributions alphabetically ...................................................................... Documentation: order distributions alphabetically Change-Id: Iaca67107cbd1e54072aed37e2e7eeb727e9e17b8 Signed-off-by: Markus Meissner <coder(a)safemailbox.de> --- M Documentation/distributions.md 1 file changed, 19 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/78871/1 diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 3185e0b..1134970 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -66,14 +66,6 @@ ## After-market firmware -### Libreboot - -[Libreboot](https://libreboot.org) is a downstream coreboot distribution that -provides ready-made firmware images for supported devices: those which can be -built entirely from source code. Their copy of the coreboot repository is -therefore stripped of all devices that require binary components to boot. - - ### Dasharo [Dasharo](https://dasharo.com/) is an open-source based firmware distribution @@ -84,18 +76,6 @@ Contributions are welcome, [this document](https://docs.dasharo.com/ways-you-can-help-us/). -### MrChromebox - -[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware -images for the vast majority of x86-based Chromebooks and Chromeboxes, using -edk2 as the payload to provide a modern UEFI bootloader. Why replace -coreboot with coreboot? Mr Chromebox's images are built using upstream -coreboot (vs Google's older, static tree/branch), include many features and -fixes not found in the stock firmware, and offer much broader OS compatibility -(i.e., they run Windows as well as Linux). They also offer updated CPU -microcode, as well as firmware updates for the device's embedded controller -(EC). This firmware "takes the training wheels off" your ChromeOS device :) - ### Heads [Heads](http://osresearch.net) is an open source custom firmware and OS @@ -109,6 +89,25 @@ of specific hardware platforms and flash security features with custom coreboot firmware and a Linux boot loader in ROM. +### Libreboot + +[Libreboot](https://libreboot.org) is a downstream coreboot distribution that +provides ready-made firmware images for supported devices: those which can be +built entirely from source code. Their copy of the coreboot repository is +therefore stripped of all devices that require binary components to boot. + +### MrChromebox + +[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware +images for the vast majority of x86-based Chromebooks and Chromeboxes, using +edk2 as the payload to provide a modern UEFI bootloader. Why replace +coreboot with coreboot? Mr Chromebox's images are built using upstream +coreboot (vs Google's older, static tree/branch), include many features and +fixes not found in the stock firmware, and offer much broader OS compatibility +(i.e., they run Windows as well as Linux). They also offer updated CPU +microcode, as well as firmware updates for the device's embedded controller +(EC). This firmware "takes the training wheels off" your ChromeOS device :) + ### Skulls [Skulls](https://github.com/merge/skulls) provides firmware images for -- To view, visit https://review.coreboot.org/c/coreboot/+/78871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaca67107cbd1e54072aed37e2e7eeb727e9e17b8 Gerrit-Change-Number: 78871 Gerrit-PatchSet: 1 Gerrit-Owner: Markus Meissner Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing entry to soc_acpi_name()
by Felix Singer (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Matt DeVillier. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78869?usp=email ) Change subject: soc/intel/cannonlake: Add missing entry to soc_acpi_name() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Gerrit-Change-Number: 78869 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Nov 2023 22:51:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing min sleep state for thermal device
by Felix Singer (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Matt DeVillier. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78868?usp=email ) Change subject: soc/intel/cannonlake: Add missing min sleep state for thermal device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Gerrit-Change-Number: 78868 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Nov 2023 22:51:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/cmn/gfx: Join MBUS while FSP-S performs GFX init
by Nick Vaccaro (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Eric Lai, Kapil Porwal, Subrata Banik. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78802?usp=email ) Change subject: soc/intel/cmn/gfx: Join MBUS while FSP-S performs GFX init ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78802?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50d719a286722f5aafbad48ab4ca60500c836dd6 Gerrit-Change-Number: 78802 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Nov 2023 22:44:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions
by Felix Singer (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78215?usp=email to look at the new patch set (#4). Change subject: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions ...................................................................... util/crossgcc/buildgcc: Fix detection of GNAT on recent versions gnatgcc is deprecated and in recent GCC releases its purpose is fulfilled by the gcc binary. In case of a deprecated gnatgcc version is installed, it doesn't provide the expected output and hostcc_has_gnat1() fails. In this case, just set the value of CC to gcc. It's still required to install GNAT in addition to GCC. Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/78215/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Gerrit-Change-Number: 78215 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions
by Felix Singer (Code Review) 01 Nov '23

01 Nov '23

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78215?usp=email ) Change subject: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions ...................................................................... Patch Set 3: (1 comment) This change is ready for review. File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/78215/comment/87a5f660_83eabf97 : PS1, Line 313: gnatbind > We still need to install the gnat package. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/78215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Gerrit-Change-Number: 78215 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Nov 2023 22:31:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/puff/var/*: Set LAN/WLAN device type to generic
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78870?usp=email ) Change subject: mb/google/puff/var/*: Set LAN/WLAN device type to generic ...................................................................... mb/google/puff/var/*: Set LAN/WLAN device type to generic Change the LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices function correctly under Windows and Linux. Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb 11 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/78870/1 diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 8b6a9ae..93e1c04 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -396,7 +396,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 6a32bdc..b7a9674 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -323,7 +323,7 @@ device pci 1d.5 on chip drivers/wifi/generic register "wake" = "GPE0_DW1_01" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[13]" = "1" end # PCI Express Port 14 (x4) diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index b1c50a2..4681e5e 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -455,7 +455,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 83f0c16..91d7482 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -429,7 +429,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 6458f9f..da76487 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -426,7 +426,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 6a2dd7b..19f0823 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -455,7 +455,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index a89c56d..9c6ea64 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -428,7 +428,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 91a19397..b81c4e4 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -366,7 +366,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index 3cd6a01..5183202 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -390,7 +390,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 5462e9b..4c13e61 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -406,7 +406,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 60ba0bc..de3704c 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -391,7 +391,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/78870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39 Gerrit-Change-Number: 78870 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing entry to soc_acpi_name()
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78869?usp=email ) Change subject: soc/intel/cannonlake: Add missing entry to soc_acpi_name() ...................................................................... soc/intel/cannonlake: Add missing entry to soc_acpi_name() The device name for the SA thermal/DPTF PCI device was missing from soc_acpi_name(), leading to an invalid PLI device constraint entry being generated in the SSDT (the name field was blank/missing). Add the missing entry, matching the name to the existing ACPI device. TEST=build/boot Win11 on google/puff (wyvern) without a BSOD. Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/78869/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 7d40634..2dc39b6 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -80,6 +80,7 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_IGD: return "GFX0"; + case SA_DEVFN_TS: return "TCPU"; case PCH_DEVFN_ISH: return "ISHB"; case SA_DEVFN_GNA: return "GNA"; case PCH_DEVFN_XHCI: return "XHCI"; -- To view, visit https://review.coreboot.org/c/coreboot/+/78869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Gerrit-Change-Number: 78869 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing min sleep state for thermal device
by Matt DeVillier (Code Review) 01 Nov '23

01 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78868?usp=email ) Change subject: soc/intel/cannonlake: Add missing min sleep state for thermal device ...................................................................... soc/intel/cannonlake: Add missing min sleep state for thermal device Add an entry in the min_pci_sleep_states array for SA_DEVFN_THERMAL, to correct warning in cbmem log: [WARN] unknown min d_stte for PCI device 00:12.0 TEST=build/boot google/puff (wyvern), verify warning not present in cbmem log, verify entry for THRM device in ACPI LPI constraint list. Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/78868/1 diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index ff93e2a..1545d19 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -170,6 +170,7 @@ { SA_DEVFN_TS, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_THERMAL, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_UFS, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_GSPI2, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_ISH, ACPI_DEVICE_SLEEP_D3 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/78868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Gerrit-Change-Number: 78868 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: util/docker: Add libnss3-dev package to coreboot-sdk for vboot
by Martin L Roth (Code Review) 01 Nov '23

01 Nov '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78867?usp=email ) Change subject: util/docker: Add libnss3-dev package to coreboot-sdk for vboot ...................................................................... util/docker: Add libnss3-dev package to coreboot-sdk for vboot The latest updates to Vboot use libnss, so add the library to the coreboot sdk. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iee0c44296b189b5327ef8f950b1bba9eb668f298 --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/78867/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index be60545..daced1b 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -51,6 +51,7 @@ libgpiod-dev \ libjaylink-dev \ liblzma-dev \ + libnss3-dev \ libncurses-dev \ libpci-dev \ libreadline-dev \ -- To view, visit https://review.coreboot.org/c/coreboot/+/78867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee0c44296b189b5327ef8f950b1bba9eb668f298 Gerrit-Change-Number: 78867 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2023