coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by Julius Werner (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Milosevic, Lean Sheng Tan, Martin L Roth, Maximilian Brune, Nico Huber. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74798/comment/bf6f793e_d2523a03 : PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards. > Just to make sure we're on the same page: We actually think it's wrong. We do it […] I mean... I'll be honest, I think this is the wrong way, I'm just giving in here because I got the impression that everyone wants this and there is no other way and I don't want to be the guy standing in the way of supporting more platforms. If there are more objections from a wider group of people then maybe we really need to have a more fundamental discussion of whether we want to allow using coreboot in this way (ramstage-only on top of other platform firmware) or not. Should we maybe open a thread on the mailing list for this, or put it on the agenda for the next leadership meeting? File src/arch/arm64/Kconfig: https://review.coreboot.org/c/coreboot/+/74798/comment/560a9fd7_64ae130a : PS6, Line 30: 1 (EL1), 2 (EL2) and 3 (EL3) These are standard Arm architectural terms (like "CPL0" on x86), I don't think we need to add more explanation here since the people that need this should know how that works anyway. I agree it would be good to add a sort of > By default, coreboot is the first firmware that runs on the system and should thus always run at EL3. This option is only provided for edge-case platforms that require running a different firmware before coreboot which drops to a lower exception level. though. https://review.coreboot.org/c/coreboot/+/74798/comment/33bdd812_0052994c : PS6, Line 41: depends on ARCH_RAMSTAGE_ARM64 May want to add a `depends on ARM64_CURRENT_EL == 3` here, since this wouldn't work for other levels. File src/arch/arm64/armv8/cpu.S: https://review.coreboot.org/c/coreboot/+/74798/comment/b3ec4c8a_0e1f4e14 : PS6, Line 87: #endif Doing this everywhere looks pretty ugly. Can we add a macro like ``` #if CONFIG_ARM64_CURRENT_EL == 1 #define CURRENT_EL(reg) reg##_el1 #elif CONFIG_ARM64_CURRENT_EL == 2 #define CURRENT_EL(reg) reg##_el2 #elif CONFIG_ARM64_CURRENT_EL == 3 #define CURRENT_EL(reg) reg##_el3 #else #error "Invalid setting for CONFIG_ARM64_CURRENT_EL!" #endif ``` to <arch/asm.h> and then use that everywhere instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 6 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 00:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: OpTee: mt8188: Let BL32 image loading from rootfs
by Kiwi Liu (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78801?usp=email to look at the new patch set (#8). Change subject: OpTee: mt8188: Let BL32 image loading from rootfs ...................................................................... OpTee: mt8188: Let BL32 image loading from rootfs For HW DRM on ARM we want to load the BL32 image from the rootfs rather than including it in the firmware. This commit is for loading of BL32 image from rootfs. BUG=b:246837563 TEST=make # select geralt Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.com> --- M src/soc/mediatek/mt8188/Kconfig M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/soc.c 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/78801/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78801?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Gerrit-Change-Number: 78801 Gerrit-PatchSet: 8 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: 3rdparty/libgfxinit: Update submodule to upstream main
by Felix Singer (Code Review) 02 Nov '23

02 Nov '23

Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/78885?usp=email ) Change subject: 3rdparty/libgfxinit: Update submodule to upstream main ...................................................................... 3rdparty/libgfxinit: Update submodule to upstream main Updating from commit id a4be8a2: 2023-08-01 10:03:33 +0000 - (Avoid warning '"Pos32" is already use-visible') to commit id 87469f2: 2023-09-21 09:21:18 +0000 - (gma config: Add new device IDs for Raptor Lake) This brings in 2 new commits: 87469f2 gma config: Add new device IDs for Raptor Lake e096913 connector_info: Fix HDMI/DVI default bytes per color setting Change-Id: I03c204dd236564525d22aebaa5262b2db51ddcb4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78885/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03c204dd236564525d22aebaa5262b2db51ddcb4 Gerrit-Change-Number: 78885 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: Update libgfxinit submodule to upstream main
by Felix Singer (Code Review) 02 Nov '23

02 Nov '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78885?usp=email ) Change subject: Update libgfxinit submodule to upstream main ...................................................................... Update libgfxinit submodule to upstream main Updating from commit id a4be8a2: 2023-08-01 10:03:33 +0000 - (Avoid warning '"Pos32" is already use-visible') to commit id 87469f2: 2023-09-21 09:21:18 +0000 - (gma config: Add new device IDs for Raptor Lake) This brings in 2 new commits: 87469f2 gma config: Add new device IDs for Raptor Lake e096913 connector_info: Fix HDMI/DVI default bytes per color setting Change-Id: I03c204dd236564525d22aebaa5262b2db51ddcb4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/78885/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index a4be8a2..87469f2 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit a4be8a21b0e2c752da0042c79aae5942418f53e2 +Subproject commit 87469f2ec0028f26ea54021ad02a94f9b1ee7759 -- To view, visit https://review.coreboot.org/c/coreboot/+/78885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03c204dd236564525d22aebaa5262b2db51ddcb4 Gerrit-Change-Number: 78885 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: util/docker: Add libnss3-dev package to coreboot-sdk for vboot
by Julius Werner (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Felix Singer, Martin L Roth. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78867?usp=email ) Change subject: util/docker: Add libnss3-dev package to coreboot-sdk for vboot ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/78867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee0c44296b189b5327ef8f950b1bba9eb668f298 Gerrit-Change-Number: 78867 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 00:24:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: OpTee: mt8188: mt8195: Let BL32 image loading from rootfs
by Kiwi Liu (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Hung-Te Lin, Kiwi Liu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78801?usp=email to look at the new patch set (#6). Change subject: OpTee: mt8188: mt8195: Let BL32 image loading from rootfs ...................................................................... OpTee: mt8188: mt8195: Let BL32 image loading from rootfs For HW DRM on ARM we want to load the BL32 image from the rootfs rather than including it in the firmware. This commit is for loading of BL32 image from rootfs. BUG=b:246837563 TEST=make # select geralt Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.com> --- M src/soc/mediatek/mt8188/Kconfig M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/soc.c M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/soc.c 6 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/78801/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/78801?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9 Gerrit-Change-Number: 78801 Gerrit-PatchSet: 6 Gerrit-Owner: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Add PPTT support
by Nico Huber (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 9: (1 comment) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/15cc3dc5_3149c8bc : PS8, Line 127: setup_topology(node->sibling, parent_ref, current); > Would separating the recursion into a pair of functions, one for node->sibling and one for node->chi […] It's not only about understanding what the program is supposed to do but also about how things look like on the stack. I know recursion is an elegant programming technique and it's used first-class in many languages. But this is C and we have a limited (8KiB, sometimes more) stack. Using recursion to descend into a tree is absolutely fine as long as we know the tree isn't too deep (they usually aren't). But walking a list that may be longer can easily eat up our stack space. I don't know how many sibling cores to expect with current processors or in the next few years. But I'm convinced already that it won't scale well. Also, because the termination is decided at runtime, tools can't warn us at build time about the stack usage. Just as an excercise I tried to picture how this looks like at runtime. First I thought, it's just the highest number of siblings (times the stack frame size ofc.). But no, there's also the other recursion, so it's the highest number of siblings plus the depth of the tree? No, if I'm not mistaken, it's the sum of the number of siblings on all levels plus the depth of the tree (assuming a homogenous tree). So how much will this be? Will we get close to 100 in the next few years? How big is the stack frame? Let's assume 32B (on a 64-bit system that seems possible). Then, oops, half our stack may be used already by the recursion. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 9 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 00:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78873?usp=email ) Change subject: mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic ...................................................................... mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic Change the dGPU/LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=untested Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/aurash/overridetree.cb M src/mainboard/google/brya/variants/brask/overridetree.cb M src/mainboard/google/brya/variants/constitution/overridetree.cb M src/mainboard/google/brya/variants/gaelin/overridetree.cb M src/mainboard/google/brya/variants/gladios/overridetree.cb M src/mainboard/google/brya/variants/gothrax/overridetree.cb M src/mainboard/google/brya/variants/hades/overridetree.cb M src/mainboard/google/brya/variants/joxer/overridetree.cb M src/mainboard/google/brya/variants/kinox/overridetree.cb M src/mainboard/google/brya/variants/kuldax/overridetree.cb M src/mainboard/google/brya/variants/lisbon/overridetree.cb M src/mainboard/google/brya/variants/marasov/overridetree.cb M src/mainboard/google/brya/variants/moli/overridetree.cb M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/osiris/overridetree.cb M src/mainboard/google/brya/variants/pujjo/overridetree.cb M src/mainboard/google/brya/variants/quandiso/overridetree.cb M src/mainboard/google/brya/variants/xivu/overridetree.cb M src/mainboard/google/brya/variants/yaviks/overridetree.cb M src/mainboard/google/brya/variants/yavilla/overridetree.cb 21 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/78873/1 diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 52b9fcd..7bea703 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -88,7 +88,7 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 alias dgpu on end + device generic 0 alias dgpu on end end device ref dtt on chip drivers/intel/dptf @@ -232,7 +232,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end #RTL8111H Ethernet NIC device ref pcie_rp4 off end diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index 2b9ebfe..09f7c66 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -163,7 +163,7 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 on end + device generic 0 on end end # IntelI225V Ethernet NIC device ref pcie_rp7 on chip drivers/net @@ -171,7 +171,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 off end #pcie_rp 8 Empty diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 995f20c..a8393b4 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -78,7 +78,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8125 Ethernet NIC device ref pcie4_0 on diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index c6083f1..41d5022 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -181,7 +181,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8125 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index b3af7c1..d198530 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -230,7 +230,7 @@ register "customized_leds" = "0x0843" register "wake" = "GPE0_DW0_07" #GPP_A7 register "device_index" = "0" - device pci 00.0 on end + device generic 0 on end end end #PCIE7 RTL8111K Ethernet NIC device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 6a21f2a..0aa0e75 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -190,7 +190,7 @@ register "customized_leds" = "0x060f" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index 87a2b48..e51c1fb 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -330,7 +330,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index b8a69a0..53ef892 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -78,7 +78,7 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 alias dgpu on end + device generic 0 alias dgpu on end end device ref dtt on chip drivers/intel/dptf @@ -239,7 +239,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end #RTL8111H Ethernet NIC device ref pcie_rp9 on diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb index 187afe5..cfa022c 100644 --- a/src/mainboard/google/brya/variants/joxer/overridetree.cb +++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb @@ -326,7 +326,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 off end # PCIE7 no SD card diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index fcca3d8..71d0e27 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -247,7 +247,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" @@ -278,7 +278,7 @@ register "wake" = "GPE0_DW0_07" #GPP_A7 register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index a6adecf..6db03ac 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -207,7 +207,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8125 and RTL8111K Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 6a21f2a..0aa0e75 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -190,7 +190,7 @@ register "customized_leds" = "0x060f" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 7fd0ef1..311971f 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -318,7 +318,7 @@ }" chip drivers/wifi/generic register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index e636540..5397463 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -164,7 +164,7 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 on end + device generic 0 on end end # IntelI225V Ethernet NIC device ref pcie_rp7 on chip drivers/net @@ -172,7 +172,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 9d9b871..5de5c1b 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -209,7 +209,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pch_espi on diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index 650d508..5ba725b 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -281,7 +281,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end # Enable PCIE 7 using clk 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 51383e0..59ab871 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -673,7 +673,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index e94d3da..64cd862 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -398,7 +398,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index be4d8df..2e781a2 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -376,7 +376,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index 308ed10..580181c 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -450,7 +450,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index ee5a3b6..4a96742 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -496,7 +496,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 off end #PCIE7 no SD card -- To view, visit https://review.coreboot.org/c/coreboot/+/78873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Gerrit-Change-Number: 78873 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: Kconfig: Restore HEAP_SIZE overrides greater than 512 KiB
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Bill XIE, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nico Huber. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78815?usp=email ) Change subject: Kconfig: Restore HEAP_SIZE overrides greater than 512 KiB ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I would put this commit first, so there are no further, intermediate regressions. Any reason not to merge it with the previous patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/78815?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78cd56b0683dd2ef94319a98a720f2da58151626 Gerrit-Change-Number: 78815 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Nov 2023 23:30:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/braswell: Unify DPTF enablement
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Matt DeVillier, Michał Żygowski, Nico Huber, Piotr Król. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78743?usp=email ) Change subject: soc/intel/braswell: Unify DPTF enablement ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Gerrit-Change-Number: 78743 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 01 Nov 2023 23:29:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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