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Change subject: soc/intel/cannonlake: Add missing min sleep state for thermal device
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly
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Patch Set 5: Code-Review+2
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Change subject: mb/google/puff/var/*: Set LAN/WLAN device type to generic
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78870/comment/c1d2028c_3997da2f :
PS1, Line 12: does
Seems wrong here
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Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/78886?usp=email )
Change subject: 3rdparty/arm-trusted-firmware: Update submodule to upstream master
......................................................................
3rdparty/arm-trusted-firmware: Update submodule to upstream master
Updating from commit id 37366af8d:
2023-07-28 17:04:54 +0200 - (Merge "fix(cpus): fix minor issue seen with a9 cpu" into integration)
to commit id 88b2d8134:
2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration)
This brings in 225 new commits.
Change-Id: I97147fbec5c0a91daab67524027f57962f61d0a1
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/78886/2
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78886?usp=email )
Change subject: Update arm-trusted-firmware submodule to upstream master
......................................................................
Update arm-trusted-firmware submodule to upstream master
Updating from commit id 37366af8d:
2023-07-28 17:04:54 +0200 - (Merge "fix(cpus): fix minor issue seen with a9 cpu" into integration)
to commit id 88b2d8134:
2023-09-06 11:26:32 +0200 - (Merge "fix(scmi): add parameter for plat_scmi_clock_rates_array" into integration)
This brings in 225 new commits.
Change-Id: I97147fbec5c0a91daab67524027f57962f61d0a1
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/78886/1
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 37366af..88b2d81 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 37366af8d4b33213abf7acb3b0523d9a3510fb52
+Subproject commit 88b2d81345dfd84902aae586a743d00ac5df2f48
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Change subject: Revert "soc/intel/{tigerlake,meteorlake}: Check ITBT FW version"
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS7:
> > Done […]
Earlier I did not test with a TBT device connected.
I will see if I can find a TBT device and verify this CL on Rex.
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Change subject: util/docker: Add libnss3-dev package to coreboot-sdk for vboot
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Patch Set 1: Code-Review+2
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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78801?usp=email
to look at the new patch set (#9).
Change subject: mt8188: Let BL32 image loading from rootfs
......................................................................
mt8188: Let BL32 image loading from rootfs
For HW DRM on ARM we want to load the BL32 image from the rootfs rather than including it in the firmware.
This commit is for loading of BL32 image from rootfs.
BUG=b:246837563
TEST=make # select geralt
Change-Id: Ic38c8beb59c090ae56c5be6821dd8625435609e9
Signed-off-by: Kiwi Liu <kiwi.liu(a)mediatek.com>
---
M src/soc/mediatek/mt8188/Kconfig
M src/soc/mediatek/mt8188/Makefile.inc
M src/soc/mediatek/mt8188/soc.c
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/78801/9
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Change subject: acpi: Add PPTT support
......................................................................
Patch Set 9:
(3 comments)
Patchset:
PS9:
> Kconfig LGTM. […]
will do
File src/acpi/acpi_pptt.c:
https://review.coreboot.org/c/coreboot/+/78071/comment/bc524039_a4260d28 :
PS8, Line 127: setup_topology(node->sibling, parent_ref, current);
> It's not only about understanding what the program is supposed to do but […]
You are right. I will replace the sibling recursion with the proposed loop :)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/78071/comment/52e7e62f_8f08cf39 :
PS9, Line 1392: /* As defined in ACPI 6.4 */
> Not really a complaint about this patch, but maybe it's time to start looking at splitting up this h […]
Good suggestion. I would prefer having separate headers, but I think we should split it (along with all the other tables like hpet, ...) in another patch.
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Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74798/comment/bf6f793e_d2523a03 :
PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards.
> Just to make sure we're on the same page: We actually think it's wrong. We do it […]
I mean... I'll be honest, I think this is the wrong way, I'm just giving in here because I got the impression that everyone wants this and there is no other way and I don't want to be the guy standing in the way of supporting more platforms. If there are more objections from a wider group of people then maybe we really need to have a more fundamental discussion of whether we want to allow using coreboot in this way (ramstage-only on top of other platform firmware) or not.
Should we maybe open a thread on the mailing list for this, or put it on the agenda for the next leadership meeting?
File src/arch/arm64/Kconfig:
https://review.coreboot.org/c/coreboot/+/74798/comment/560a9fd7_64ae130a :
PS6, Line 30: 1 (EL1), 2 (EL2) and 3 (EL3)
These are standard Arm architectural terms (like "CPL0" on x86), I don't think we need to add more explanation here since the people that need this should know how that works anyway. I agree it would be good to add a sort of
> By default, coreboot is the first firmware that runs on the system and should thus always run at EL3. This option is only provided for edge-case platforms that require running a different firmware before coreboot which drops to a lower exception level.
though.
https://review.coreboot.org/c/coreboot/+/74798/comment/33bdd812_0052994c :
PS6, Line 41: depends on ARCH_RAMSTAGE_ARM64
May want to add a `depends on ARM64_CURRENT_EL == 3` here, since this wouldn't work for other levels.
File src/arch/arm64/armv8/cpu.S:
https://review.coreboot.org/c/coreboot/+/74798/comment/b3ec4c8a_0e1f4e14 :
PS6, Line 87: #endif
Doing this everywhere looks pretty ugly. Can we add a macro like
```
#if CONFIG_ARM64_CURRENT_EL == 1
#define CURRENT_EL(reg) reg##_el1
#elif CONFIG_ARM64_CURRENT_EL == 2
#define CURRENT_EL(reg) reg##_el2
#elif CONFIG_ARM64_CURRENT_EL == 3
#define CURRENT_EL(reg) reg##_el3
#else
#error "Invalid setting for CONFIG_ARM64_CURRENT_EL!"
#endif
```
to <arch/asm.h> and then use that everywhere instead?
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