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Change subject: commonlib: Add GCD function
......................................................................
commonlib: Add GCD function
Implement a simple GCD function.
BUG=b:307790895
TEST=emerge-geralt coreboot
TEST=make tests/commonlib/bsd/gcd-test
Change-Id: I21819cda4299b3809b8ca7a95cbdc6a87e4b3481
Signed-off-by: Yidi Lin <yidilin(a)chromium.org>
---
M src/commonlib/Makefile.inc
A src/commonlib/bsd/gcd.c
A src/commonlib/bsd/include/commonlib/bsd/gcd.h
M tests/commonlib/bsd/Makefile.inc
A tests/commonlib/bsd/gcd-test.c
5 files changed, 54 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/78798/3
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78310?usp=email )
Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/marasov/variant.c:
https://review.coreboot.org/c/coreboot/+/78310/comment/8566f09f_fbd4bc6c :
PS2, Line 13: printk(BIOS_INFO, "Use wifi_sar_1.hex.\n");
> do we really need this msg ?
I think this follow other projects LoL.
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Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
......................................................................
Patch Set 2:
(3 comments)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/78310/comment/325c7e6d_940f2863 :
PS2, Line 275: select CHROMEOS_WIFI_SAR if CHROMEOS
please follow the alphabetic order please?
File src/mainboard/google/brya/variants/marasov/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/78310/comment/7b16b225_01475e25 :
PS2, Line 20: option WIFI_SAR_ID_0 0
what is the usage of this FW config ?
is it more like `absent` ?
File src/mainboard/google/brya/variants/marasov/variant.c:
https://review.coreboot.org/c/coreboot/+/78310/comment/779deb67_6292eacb :
PS2, Line 13: printk(BIOS_INFO, "Use wifi_sar_1.hex.\n");
do we really need this msg ?
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Change subject: drivers/pc80/tpm: probe for TPM family of a device
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/76955/comment/59d2a2ea_2e13d430 :
PS2, Line 92: tpm_family
> Is it? I think all TPM1. […]
Sorry for responding soo late. Since TCG uses 'family' as well we can keep it. Sorry for the noise.
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Change subject: doc/soc/intel/xeon_sp: Add Xeon Scalable processor coreboot community preview guide
......................................................................
Patch Set 5: Code-Review+1
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Change subject: mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic
......................................................................
Patch Set 1: Code-Review+2
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Kyösti Mälkki, Matt DeVillier, Nico Huber, Patrick Georgi, Paul Menzel, Subrata Banik, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
......................................................................
Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
Commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large
value") breaks S3 resume from TSEG stage cache on many platforms,
including GM45 and Ivy Bridge, so limit it to 512 KiB.
HEAP_SIZE overrides greater than 512K prior to commit 44a48ce7a46c are
restored.
Please test this against other platforms before merging!
Tested: Setting it to 0x80000 results a working S3 resume on Thinkpad
X200 and T430, with log in cbmem for S3 resume, while 0xa0000
breaks it. coreboot log during failed resume when (HEAP_SIZE
>= 0xa0000) cannot be obtained from EHCI debug, while log in
cbmem shows that ramstage is failed to be found in TSEG stage
cache, as shown in https://ticket.coreboot.org/issues/512 .
Resolves: https://ticket.coreboot.org/issues/512
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: Ib1de1eb8487df5bdf004e544d40667833a291515
---
M src/Kconfig
M src/northbridge/amd/pi/Kconfig
M src/soc/amd/picasso/Kconfig
M src/soc/amd/stoneyridge/Kconfig
4 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/78623/13
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Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78815?usp=email )
Change subject: Kconfig: Restore HEAP_SIZE overrides greater than 512 KiB
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Any reason not to merge it with the previous patch?
@Paul Menzel once suggested to separate these.
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Bill XIE has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78815?usp=email )
Change subject: Kconfig: Restore HEAP_SIZE overrides greater than 512 KiB
......................................................................
Abandoned
Combined back to the previous one.
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