Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77588?usp=email )
Change subject: mb/google/brya/var/quandiso: Add VBT data file
......................................................................
mb/google/brya/var/quandiso: Add VBT data file
Add data.vbt file for quandiso recovery image. Select INTEL_GMA_HAVE_VBT
for quandiso as it has a VBT file now. The VBT file is copied from
chromeos internal source and based on yaviks VBT.
BUG=b:296506936
TEST=emerge-nissa coreboot
Change-Id: Ia9f84b4f56171737a9e7a513b63549b3013775c4
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77588
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Shawn Ku <shawnku(a)google.com>
---
M src/mainboard/google/brya/Kconfig
A src/mainboard/google/brya/variants/quandiso/data.vbt
2 files changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Shawn Ku: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 8c5e707..683f917 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -359,6 +359,7 @@
select DRIVERS_I2C_SX9324
select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
select HAVE_WWAN_POWER_SEQUENCE
+ select INTEL_GMA_HAVE_VBT
config BOARD_GOOGLE_REDRIX
select BOARD_GOOGLE_BASEBOARD_BRYA
diff --git a/src/mainboard/google/brya/variants/quandiso/data.vbt b/src/mainboard/google/brya/variants/quandiso/data.vbt
new file mode 100644
index 0000000..be9411d
--- /dev/null
+++ b/src/mainboard/google/brya/variants/quandiso/data.vbt
Binary files differ
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Change subject: mb/google/rex: Enable sending EOP from payload
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/rex/Kconfig:
https://review.coreboot.org/c/coreboot/+/78649/comment/a73c87b2_270145b7 :
PS4, Line 31: select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
Instead of making this a select, could we enable it as a default instead? There are a lot of "depends on" statements in this option, and a select will override all of them and just force it to be enabled, even if the requirements are not met.
Additionally, we'd like to be able to support a non-chromeos build that doesn't use depthcharge, and still support sending the EOP.
You'd want something like this down in the main section protected by `if BOARD_GOOGLE_REX_COMMON`
```
config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
prompt "Send End of Post message in the payload"
default y if CHROMEOS
config SOC_INTEL_CSE_SEND_EOP_ASYNC
default y if !SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD
```
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Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78791?usp=email )
Change subject: mb/google/nissa: Add AUDIO_CONFIG in fw_config
......................................................................
mb/google/nissa: Add AUDIO_CONFIG in fw_config
The codec alc5650 has different setting from other amp codec in
depthcharge. Since nissa has a single shared depthcharge target,
add the fw_config field to allow different audio_configs.
(refer to chromium:4983866)
BUG=b:307410704
TEST=With depthcharge change, set fw_config and gbb flags on craaskana
and check beep sound on firmware screen is workable.
Change-Id: I7446fce57557204d91151f1a31755381c1813c6f
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78791
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Reka Norman <rekanorman(a)chromium.org>
Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
Ren Kuo: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Tyler Wang: Looks good to me, but someone else must approve
Reka Norman: Looks good to me, approved
David Wu: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
index ad5b1f8..55bd9c0 100644
--- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
@@ -1,4 +1,8 @@
fw_config
+ field AUDIO_CONFIG 28
+ option AMP_GPIO 0
+ option AMP_RT5650 1
+ end
field SD_BOOT 29
option SD_BOOT_ENABLE 0
option SD_BOOT_DISABLE 1
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Change subject: soc/intel/cmn/block/cse: Support sending EOP from payload
......................................................................
Patch Set 12:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/74765/comment/416cc318_a77540fa :
PS12, Line 144: help
Maybe add a depends on CHROMEOS and/or other payloads that support sending EOP?
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Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly
......................................................................
Patch Set 4: Code-Review+2
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Change subject: arch/x86/memcpy.c: Optimize code for 64bit
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
File src/arch/x86/memcpy.c:
https://review.coreboot.org/c/coreboot/+/78646/comment/6c9af60a_f515b7d7 :
PS2, Line 30: : "=&c" (d0), "=&D" (d1), "=&S" (d2)
> Done
Good catch Jérémy, thanks!
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Change subject: acpi.c: Fix generating pointer to cb_tables located >4G
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS2:
> I'm not sure what you mean. There is no 64bit equivalent of Memory32Fixed in ACPI.
Right, but Memory32Fixed is also just a shorthand for a resource report, IIRC.
So what I meant, I guess, was that we could have a acpigen_write_mem64fixed()
that does exactly what you do on the else path, just shares the interface with
the mem32 version.
OTOH, now that I looked into how the functions are implemented, I noticed
acpigen_resource_producer_mmio() already has a 32-bit check. So the cleanest
C code would probably be to just call that unconditionally (but would waste
a few bytes in the SSDT in the 32-bit case).
(obviously there are too many ways to do it)
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Change subject: lib: Add GCD function
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/78798/comment/daa32620_78f6b331 :
PS2, Line 7: lib: Add GCD function
path is no longer "lib"
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Change subject: lib: Add GCD function
......................................................................
Patch Set 2:
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Patchset:
PS2:
Can we add some tests?
File src/commonlib/bsd/gcd.c:
https://review.coreboot.org/c/coreboot/+/78798/comment/6248e1e9_20110851 :
PS2, Line 6: unsigned long gcd(unsigned long a, unsigned long b)
Change to uint64_t to allow larger values?
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Change subject: soc/intel/braswell: Unify DPTF enablement
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/cyan/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/78743/comment/19ec560e_99b73cec :
PS2, Line 98: off
> > strago is currently set to on / I didn't change it, just corrected the comment to make it consiste […]
I went ahead and set cyan to ON, I'll add another commit to disable it as the previous one wasn't really intentional in disabling DPTF, just "unused devices"
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Gerrit-MessageType: comment