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Change subject: Kconfig: Restore HEAP_SIZE overrides greater than 512 KiB
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
I would put this commit first, so there are no further, intermediate regressions.
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Change subject: Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
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Patch Set 10: Code-Review+1
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Change subject: acpi: Add PPTT support
......................................................................
Patch Set 8:
(7 comments)
Patchset:
PS8:
This is nice code overall. Please don't mind the long comments,
these ACPI things are sometimes hard to get right from the start.
File src/acpi/acpi_pptt.c:
https://review.coreboot.org/c/coreboot/+/78071/comment/892443d4_4e280bd2 :
PS6, Line 66:
> Is that really necessary? I mean, Jenkins does not complain and it really is only a matter of prefer […]
I agree with Arthur here.
While the style guide is not explicit about this, it does argue against
unnecessary empty lines. It's also uncommon enough to make readers, who
are used to the kernel (and coreboot) style, stumble (for maybe a second,
I was wondering why Gerrit shows the code like this).
File src/acpi/acpi_pptt.c:
https://review.coreboot.org/c/coreboot/+/78071/comment/7835e789_1f4fdeee :
PS8, Line 13: * Disclaimer:
: *
: * The generated PPTT table might not be optimized for space, since this
: * implementation creates unique resources (caches) for each CPU provided by
: * the topology tree. Going by the ACPI 6.4 spec, this is fine. We do this to
: * avoid further edge cases and keep the logic as simple as possible.
: *
: * "though less space efficient, it is also acceptable to declare a node
: * for each instance of a resource. In the example above, it would be legal to
: * declare an L1 for each processor."
: *
: * "Compaction of identical resources must be avoided if an implementation requires
: * any resource instance to be referenced uniquely. For example, in the above example,
: * the L1 resource of each processor must be declared using a dedicated structure to
: * permit unique references to it."
: *
I found this to be more confusing than helpful. The quotes reference examples
that were not quoted, hence provide no value without reading the actual spec.
My first impression was that this is about listing, for instance, shared caches
more than once. But it is not. What the spec describes is the possibility to
compact individual resources that have the exact same characteristics.
There is a related quirk that is, IMO, much more worth to mention: The current
structures don't allow to converge lists (cf. Fig. 5.15: Cache Type Structure -
Type 1 Example; here, L1D and L1I should point to the same L2 object as next
level). I'm not sure if that is something for a comment or something to fix.
https://review.coreboot.org/c/coreboot/+/78071/comment/67a4c1f0_0449eecf :
PS8, Line 40: * the difference between the start of the PPTT table
Nit, I would call it `offset`. And TBH, I don't think we need to say
more than that "References are the offset from the start of the PPTT table.".
Drawing the picture here might make things more confusing, IMO, but I don't
mind.
https://review.coreboot.org/c/coreboot/+/78071/comment/660304db_ae4122d3 :
PS8, Line 56: u32
It's uncommon to use a fixed-size integer unless you need one (e.g. for
an external interface). Simply `unsigned int` would be preferred.
https://review.coreboot.org/c/coreboot/+/78071/comment/f45fc417_e93d239b :
PS8, Line 127: setup_topology(node->sibling, parent_ref, current);
This is just walking the list without any reference to the current
setup_topology()'s context, right? Recursion is generally something
that should only be used if necessary. And if we can avoid it here,
we should.
You can probably see clearly what is going on here, I assume Arthur
and Patrick, too. But the next person who gets to edit this code in
a year or so might not. And that's when bugs sneak in when the code
isn't written as simple as possible.
I hope I'm not wrong with this. Could this be written as follows,
with only one recursion where necessary?
```
static void setup_topology(const struct pptt_topology *node, const u32 parent_ref, unsigned long *current)
{
for (; node; node = node->sibling) {
const u32 cpu_ref = new_pptt_cpu(current, node, parent_ref);
setup_topology(node->child, cpu_ref, current);
}
}
```
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/78071/comment/369a4823_562fd0df :
PS3, Line 1442: structures
> > It looks like other platforms do not have custom data structures and instead call a function to le […]
I first leant to agree with Arthur, but it seems more delicate than one might
think. What we would want here is to design structures that are nicer to handle
in C but can still express the same as the flat ACPI ones, right?
The current structures and code, however, don't express everything ACPI can do
(cf. comment on the "Disclaimer" comment in the source). So it seems possible,
that if we don't get it right from the start, the next developer adding a
different CPU with different topology might have to overhaul the whole code
again...
Also, reusing the flags values creates redundancies. For instance, `is_leaf`
is something that is also expressed by a NULL-pointer in the structures.
To wrap this up, I don't mind merging it in this state. Just want to make it
obvious, that it won't be correct from the start unless we invest a lot more,
also to avoid to tailor this to a specific CPU. It's usually hard to get without
multiple, different, real-world examples (and right now we don't even have one
under review, AFAICS). If it's worth to even try, IDK.
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Change subject: mb/google/nissa: Add AUDIO_CONFIG in fw_config
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Patch Set 6: Code-Review+2
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Change subject: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/craaskov/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/78843/comment/2b5ce8b8_b3e03830 :
PS1, Line 5: CONFIG_FW_CONFIG
you have wifi sar which is not depend fw config.
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Change subject: soc/intel/*: Correct ACPI device name for eMMC
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Patch Set 2: Code-Review+2
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Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT
......................................................................
Patch Set 33:
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/77886/comment/e97816bb_c4c87b44 :
PS4, Line 27: cbfs_map
> > If it's like the generic heap, why have it separate?
>
> Historical reasons, and the fact that it needs to be available in pre-RAM stages. If you're asking whether we should combine it with the ramstage heap into a single malloc() API for all stages, then... maybe. There are a few gotchas (e.g. it needs special alignment requirements on a few platforms) but it could certainly be done.
>
> There might also be some concern that exposing a general malloc() API in pre-RAM stages could lead to it being abused too widely and cause out-of-memory edge cases. As long as it's only for files, there are less edge case combinations to test. There could also be the concern that if more code uses this, the chance that a file allocation can still clean up after itself gets lower (because the allocator is only able to free the last two allocations), so that might be a good reason to keep the heaps separate.
Good arguments as usual ;) That it's used pre-ramstage is probably the
difference I was missing.
>
> Anyway, probably not a question to decide on this CL.
>
> > We eventually copy the VBT to CBMEM anyway. So there shouldn't be a need to map twice.
>
> I'm not really familiar with this code but it looks like this is an exported function that has a bunch of callers outside this file (e.g. 10 just via `vbt_get()`). It's possible that something could be cleaned up and reuse the CBMEM allocation there, but probably not a small task.
Yes, never a small task in that area. I just hope we are not refactoring too
much at the edges and miss the bigger picture.
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Change subject: soc/intel/cmn/block/cse: Support sending EOP from payload
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS12:
> > Is it the overall patch that added the 10 ms or just the recent change? […]
I guess this is explainable due to the nature of how this feature works?
Sending EOP later will cost some time at CSE side, right?
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Change subject: Documentation: add Nitrokey to distributions
......................................................................
Patch Set 5:
(3 comments)
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/78299/comment/7d322b1b_34444bf3 :
PS5, Line 13: German
> lowercase
done - but as of my understanding this should be capitalized. But I might be wrong as I am no native speaker.
https://review.coreboot.org/c/coreboot/+/78299/comment/29d0cf33_309fb98a :
PS5, Line 17: edk2
> all uppercase
done
https://review.coreboot.org/c/coreboot/+/78299/comment/152114ba_3c76d02c :
PS5, Line 19: send
> typo: sen*t*
done
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Hello Felix Singer, Michał Żygowski, Patrick Georgi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78299?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+1 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: Documentation: add Nitrokey to distributions
......................................................................
Documentation: add Nitrokey to distributions
Nitrokey offers various products, which have coreboot pre-installed.
Change-Id: I3ef25e0e1cb97eda5fd457bdb650f3ee3f00210a
Signed-off-by: Markus Meissner <coder(a)safemailbox.de>
---
M Documentation/distributions.md
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/78299/6
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