coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3036 discussions

[XS] Change in coreboot[main]: util/docker: Add libnss3-dev package to coreboot-sdk for vboot
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78867?usp=email ) Change subject: util/docker: Add libnss3-dev package to coreboot-sdk for vboot ...................................................................... util/docker: Add libnss3-dev package to coreboot-sdk for vboot The latest updates to Vboot use libnss, so add the library to the coreboot sdk. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Iee0c44296b189b5327ef8f950b1bba9eb668f298 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78867 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index be60545..daced1b 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -51,6 +51,7 @@ libgpiod-dev \ libjaylink-dev \ liblzma-dev \ + libnss3-dev \ libncurses-dev \ libpci-dev \ libreadline-dev \ -- To view, visit https://review.coreboot.org/c/coreboot/+/78867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee0c44296b189b5327ef8f950b1bba9eb668f298 Gerrit-Change-Number: 78867 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78215?usp=email ) Change subject: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions ...................................................................... util/crossgcc/buildgcc: Fix detection of GNAT on recent versions gnatgcc is deprecated and in recent GCC releases its purpose is fulfilled by the gcc binary. In case of a deprecated gnatgcc version is installed, it doesn't provide the expected output and hostcc_has_gnat1() fails. In this case, just set the value of CC to gcc. It's still required to install GNAT in addition to GCC. Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78215 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M util/crossgcc/buildgcc 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ebc9fcb..d336556 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1080,7 +1080,17 @@ fi else if searchtool gnatgcc "Free Software Foundation" nofail > /dev/null; then + # gnatgcc is deprecated and in recent GCC releases its purpose is + # fulfilled by the gcc binary. In case of a deprecated gnatgcc + # version is installed, it doesn't provide the expected output and + # hostcc_has_gnat1() fails. In this case, just set the value of CC + # to gcc. + # TODO: Remove this whole branch when time is appropriate as the + # second branch fulfills our needs. CC=gnatgcc + if ! hostcc_has_gnat1; then + CC=gcc + fi elif searchtool gcc "Free Software Foundation" nofail > /dev/null; then CC=gcc else -- To view, visit https://review.coreboot.org/c/coreboot/+/78215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Gerrit-Change-Number: 78215 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Felix Singer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78215?usp=email ) Change subject: util/crossgcc/buildgcc: Fix detection of GNAT on recent versions ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/78215/comment/c285934b_6ae65ad8 : PS1, Line 1082: if searchtool gnatgcc "Free Software Foundation" nofail > /dev/null; then > Your proposal changes behavior since a value set by the user has less priority now. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c Gerrit-Change-Number: 78215 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 02 Nov 2023 16:38:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: Documentation: order distributions alphabetically
by Felix Singer (Code Review) 02 Nov '23

02 Nov '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78864?usp=email ) Change subject: Documentation: order distributions alphabetically ...................................................................... Documentation: order distributions alphabetically Change-Id: I95d4347791988087d90992b45120ff34ba2da1c5 Signed-off-by: Markus Meissner <coder(a)safemailbox.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78864 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/distributions.md 1 file changed, 35 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/distributions.md b/Documentation/distributions.md index 219c659..1134970 100644 --- a/Documentation/distributions.md +++ b/Documentation/distributions.md @@ -8,6 +8,15 @@ ## Hardware shipping with coreboot +### ChromeOS Devices + +All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes, +Chromebit, etc) released from 2012 onward use coreboot for their main system +firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware +running on the Embedded Controller (EC) – a small microcontroller which provides +functions like battery management, keyboard support, and sensor interfacing – +is open source as well. + ### Nitrokey [Nitrokey](https://nitrokey.com) is a german IT security hardware vendor which @@ -27,15 +36,6 @@ and the firmware is equipped with important security features such as measured boot, verified boot, TPM integration and UEFI Secure Boot. -### ChromeOS Devices - -All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes, -Chromebit, etc) released from 2012 onward use coreboot for their main system -firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware -running on the Embedded Controller (EC) – a small microcontroller which provides -functions like battery management, keyboard support, and sensor interfacing – -is open source as well. - ### PC Engines APUs [PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that @@ -43,6 +43,13 @@ third party, [3mdeb](https://3mdeb.com). They provide current and tested firmware binaries on [GitHub](https://pcengines.github.io). +### Purism + +[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and +security; part of that effort is to minimize the amount of proprietary and/or +binary code. Their laptops ship with a blob-free OS and coreboot firmware +with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. + ### Star Labs [Star Labs](https://starlabs.systems/) offers a range of laptops designed and @@ -57,23 +64,8 @@ Firmware](https://github.com/system76/firmware-open), an open source distribution of coreboot, edk2, and System76 firmware applications. -### Purism - -[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and -security; part of that effort is to minimize the amount of proprietary and/or -binary code. Their laptops ship with a blob-free OS and coreboot firmware -with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload. - ## After-market firmware -### Libreboot - -[Libreboot](https://libreboot.org) is a downstream coreboot distribution that -provides ready-made firmware images for supported devices: those which can be -built entirely from source code. Their copy of the coreboot repository is -therefore stripped of all devices that require binary components to boot. - - ### Dasharo [Dasharo](https://dasharo.com/) is an open-source based firmware distribution @@ -84,18 +76,6 @@ Contributions are welcome, [this document](https://docs.dasharo.com/ways-you-can-help-us/). -### MrChromebox - -[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware -images for the vast majority of x86-based Chromebooks and Chromeboxes, using -edk2 as the payload to provide a modern UEFI bootloader. Why replace -coreboot with coreboot? Mr Chromebox's images are built using upstream -coreboot (vs Google's older, static tree/branch), include many features and -fixes not found in the stock firmware, and offer much broader OS compatibility -(i.e., they run Windows as well as Linux). They also offer updated CPU -microcode, as well as firmware updates for the device's embedded controller -(EC). This firmware "takes the training wheels off" your ChromeOS device :) - ### Heads [Heads](http://osresearch.net) is an open source custom firmware and OS @@ -109,6 +89,25 @@ of specific hardware platforms and flash security features with custom coreboot firmware and a Linux boot loader in ROM. +### Libreboot + +[Libreboot](https://libreboot.org) is a downstream coreboot distribution that +provides ready-made firmware images for supported devices: those which can be +built entirely from source code. Their copy of the coreboot repository is +therefore stripped of all devices that require binary components to boot. + +### MrChromebox + +[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware +images for the vast majority of x86-based Chromebooks and Chromeboxes, using +edk2 as the payload to provide a modern UEFI bootloader. Why replace +coreboot with coreboot? Mr Chromebox's images are built using upstream +coreboot (vs Google's older, static tree/branch), include many features and +fixes not found in the stock firmware, and offer much broader OS compatibility +(i.e., they run Windows as well as Linux). They also offer updated CPU +microcode, as well as firmware updates for the device's embedded controller +(EC). This firmware "takes the training wheels off" your ChromeOS device :) + ### Skulls [Skulls](https://github.com/merge/skulls) provides firmware images for -- To view, visit https://review.coreboot.org/c/coreboot/+/78864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95d4347791988087d90992b45120ff34ba2da1c5 Gerrit-Change-Number: 78864 Gerrit-PatchSet: 3 Gerrit-Owner: Markus Meissner Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: 3rdparty/libgfxinit: Update submodule to upstream main
by Felix Singer (Code Review) 02 Nov '23

02 Nov '23

Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78885?usp=email ) Change subject: 3rdparty/libgfxinit: Update submodule to upstream main ...................................................................... Abandoned Won't have any effect without further remaining work -- To view, visit https://review.coreboot.org/c/coreboot/+/78885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03c204dd236564525d22aebaa5262b2db51ddcb4 Gerrit-Change-Number: 78885 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

[S] Change in coreboot[main]: soc/amd/*: Ensure PSP soft fuse bitmask set properly
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78823?usp=email ) Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly ...................................................................... soc/amd/*: Ensure PSP soft fuse bitmask set properly Commit e728766f4596 ("soc/amd/mendocino: Do not load MP2 Firmware when in RO") added logic to ensure that the MP2 disable soft fuse bit was set for the RO section, but failed to check if the bit was already set otherwise (as it is for non-ChromeOS builds). This caused the bit to appear twice in the PSP_RO_SOFTFUSE_BITS string, and when the string was converted to a series of numeric values and added together, bit (n+1) ended up being set instead of bit n. To mitigate this, use the makefile sort() function to ensure the PSP_[RO_]SOFTFUSE_BITS string does not contain any duplicates before the bitmask is calculated. Apply this to all AMD SoC makefiles where the softfuse bits are added. TEST=build/boot google/skyrim (frostflow). Use a verbose build (V=1) to verify that the correct soft fuse value is passed to amdfwtool for RO and RW_A/B for both ChromeOS and non-ChromeOS builds. Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78823 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/genoa/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Makefile.inc 6 files changed, 7 insertions(+), 7 deletions(-) Approvals: Felix Held: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Martin L Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index c92bb0d..044d33e 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -132,7 +132,7 @@ # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) # # Build the arguments to amdfwtool (order is unimportant). Missing file names diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index de8e2f1..506f6cf 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -74,7 +74,7 @@ # Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) # # Build the arguments to amdfwtool (order is unimportant). Missing file names diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 5b63df3..675712f 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -148,7 +148,7 @@ # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) # # Build the arguments to amdfwtool (order is unimportant). Missing file names diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index f123487..6cb098f 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -161,9 +161,9 @@ # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) PSP_RO_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_RO_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_RO_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) # # Build the arguments to amdfwtool (order is unimportant). Missing file names diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index cab8987..5641e8c 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -168,7 +168,7 @@ # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) # # Build the arguments to amdfwtool (order is unimportant). Missing file names diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 9c3dd9f..7ca25d0 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -138,7 +138,7 @@ # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. set-bit=$(call int-shift-left, 1 $(call _toint,$1)) PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) # # Build the arguments to amdfwtool (order is unimportant). Missing file names -- To view, visit https://review.coreboot.org/c/coreboot/+/78823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5 Gerrit-Change-Number: 78823 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: mb/google/brya/var/omnigul: Add fingerprint SPI
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78427?usp=email ) Change subject: mb/google/brya/var/omnigul: Add fingerprint SPI ...................................................................... mb/google/brya/var/omnigul: Add fingerprint SPI Add fingerprint SPI, and power off FPMCU during romstage. BUG=b:305860604, b:306320063 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Signed-off-by: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/google/brya/variants/omnigul/gpio.c M src/mainboard/google/brya/variants/omnigul/overridetree.cb 2 files changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/omnigul/gpio.c b/src/mainboard/google/brya/variants/omnigul/gpio.c index d3f907d..c021698 100644 --- a/src/mainboard/google/brya/variants/omnigul/gpio.c +++ b/src/mainboard/google/brya/variants/omnigul/gpio.c @@ -316,12 +316,15 @@ * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. */ PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* Enable touchscreen, hold in reset */ /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C1 : SMBDATA ==> USI_RST_L */ PAD_CFG_GPO(GPP_C1, 0, DEEP), + // D1 : ISH_GP1 ==> FP_RST_ODL / + PAD_CFG_GPO(GPP_D1, 0, DEEP), + // D2 : ISH_GP2 ==> EN_FP_PWR / + PAD_CFG_GPO(GPP_D2, 0, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index b9c6d87..0942299d 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -4,6 +4,10 @@ option STORAGE_UFS 1 option STORAGE_NVME 2 end + field FINGERPRINT 9 + option DISABLE_FP 0 + option ENABLE_FP 1 + end end chip soc/intel/alderlake @@ -318,6 +322,23 @@ device i2c 2c on end end end #I2C5 + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" + device spi 0 hidden + probe FINGERPRINT ENABLE_FP + end + end # FPMCU + end device ref pcie_rp8 off end device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Gerrit-Change-Number: 78427 Gerrit-PatchSet: 11 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[L] Change in coreboot[main]: acpi: Add PPTT support
by Nico Huber (Code Review) 02 Nov '23

02 Nov '23

1 0

[S] Change in coreboot[main]: mb/google/brya/var/omnigul: Add fingerprint SPI
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Derek Huang, Eric Lai, Jamie Chen, Nick Vaccaro, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun Tuli. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78427?usp=email ) Change subject: mb/google/brya/var/omnigul: Add fingerprint SPI ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79 Gerrit-Change-Number: 78427 Gerrit-PatchSet: 10 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 13:49:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: acpi: Add PPTT support
by Nico Huber (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Arthur Heymans, Cliff Huang, David Milosevic, Lance Zhao, Martin L Roth, Maximilian Brune, Patrick Rudolph, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email ) Change subject: acpi: Add PPTT support ...................................................................... Patch Set 9: (3 comments) File src/acpi/acpi_pptt.c: https://review.coreboot.org/c/coreboot/+/78071/comment/f91f16eb_ffecdf03 : PS8, Line 13: * Disclaimer: : * : * The generated PPTT table might not be optimized for space, since this : * implementation creates unique resources (caches) for each CPU provided by : * the topology tree. Going by the ACPI 6.4 spec, this is fine. We do this to : * avoid further edge cases and keep the logic as simple as possible. : * : * "though less space efficient, it is also acceptable to declare a node : * for each instance of a resource. In the example above, it would be legal to : * declare an L1 for each processor." : * : * "Compaction of identical resources must be avoided if an implementation requires : * any resource instance to be referenced uniquely. For example, in the above example, : * the L1 resource of each processor must be declared using a dedicated structure to : * permit unique references to it." : * > With this comment I wanted to explain, that there is still room for optimizations regarding the table size, since the current approach creates unique structures instead of compacting them, in order to reduce code complexity. And that's fine. I only find the incomplete quotes irritating, as... > > The quotes simply serve as proof, that this is, nevertheless, still valid ACPI. ...they can't prove anything on their own. If one has to read the spec anyway to make sure that the quotes were used correctly and the reasoning is sound, a simple reference might be better. I'm struggling a bit to put my general concern into words. It's somewhat like this: Describing what your code does and why is good. But when you start to justify why this is correct, you also risk to sway the reader that your own interpretation is correct. If they think "oh, these quotes explain everything already", it's like you did your own review. So, IMO, any justification should be complete and a reviewer should make sure that it really is. We may want to revisit this when the code is ready. https://review.coreboot.org/c/coreboot/+/78071/comment/264ac2dd_afb511e8 : PS8, Line 56: u32 > Although we don't populate the PPTT table directly with the return value of "count_resources", it is […] I understand and I think it should be your call. And it's really no big deal for this piece of code. In general, though, it's often best to leave decisions to the compiler (so it can optimize best) and to have overall portable code. https://review.coreboot.org/c/coreboot/+/78071/comment/a2c156f6_065a8434 : PS8, Line 127: setup_topology(node->sibling, parent_ref, current); > You are right. […] Thanks! please test, though. It will at least change the order of things in the table. -- To view, visit https://review.coreboot.org/c/coreboot/+/78071?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia119e1ba15756704668116bdbc655190ec94ff10 Gerrit-Change-Number: 78071 Gerrit-PatchSet: 9 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 13:37:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023