coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/skyrim/frostflow: Drop GPIO override for camera shutter
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Frank Wu, Jason Nien, Karthik Ramasubramanian, Martin Roth. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77678?usp=email ) Change subject: mb/google/skyrim/frostflow: Drop GPIO override for camera shutter ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > Adding ODM partner to confirm. hi Karthik, any update here? no word from Frank yet -- To view, visit https://review.coreboot.org/c/coreboot/+/77678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Gerrit-Change-Number: 77678 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 13:36:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/hatch: Don't enable the SATA controller by default
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78812?usp=email ) Change subject: mb/google/hatch: Don't enable the SATA controller by default ...................................................................... Abandoned All of the hatch boards with NVMe can also support SATA, so want to leave this enabled by default -- To view, visit https://review.coreboot.org/c/coreboot/+/78812?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b9de237a4eda90f4a6a10c2374c49bca5b041b2 Gerrit-Change-Number: 78812 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: mb/google/guybrush: Set PS2K_IRQ to level/low
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78137?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/guybrush: Set PS2K_IRQ to level/low ...................................................................... mb/google/guybrush: Set PS2K_IRQ to level/low On guybrush, keyboard presses are signaled by the EC via eSPI virtual wire. The interrupt is shared with others and should be active low. From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"): > The default state for the IRQ lines when the eSPI controller comes > out of reset is high. This is because the IRQ lines are shared with > the other IRQ sources using AND gates. This means that in order to > not cause any spurious interrupts or miss any interrupts, the > IO-APIC must use a low polarity trigger. Setting `vw_irq_polarity` in the device tree provides an option to invert interrupts from the eSPI controller, but the register is initialized from verstage which is baked into RO. As a workaround, the necessary interrupts on the EC have been reconfigured to be active low, and we can modify the IO-APIC accordingly. EC related CL here: https://crrev.com/c/4891663 BUG=b:218874489 TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage` -Flash new RW fw and verify keyboard is functional -`suspend_stress_test -c 1` and verify i8042 irq is removed as a wake source -`echo mem > /sys/power/state`. Press key and verify system wake from i8042. Cq-Depend: chromium:4891663 Change-Id: I7d093d94a666263684645ef724e945069c68c806 Signed-off-by: Mark Hasemeyer <markhas(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h 2 files changed, 5 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 848fd93..49ff8dd 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -44,12 +44,10 @@ /* * b/218874489 - This should really be ESPI_VW_IRQ_LEVEL_HIGH, - * but eSPI gets configured in verstage which is in RO. - * We have already locked RO for guybrush devices so we need - * make it so x86 coreboot re-initializes the vw_irq_polarity. - * This leaves another problem, verstage also runs in S0i3, but - * we don't run any other x86 coreboot stages, so we need to - * figure out a way to reset the eSPI polarity. + * but eSPI gets configured in verstage which is in RO, and the + * RO is already locked down. As a workaround, the EC fw has + * been modified to use active low signalling for the + * interrupts that require it. */ .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1), }" diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h index 643c534..83a4b2f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h @@ -63,6 +63,7 @@ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Level, ActiveLow, Shared) {1} /* Enable EC sync interrupt */ #define EC_ENABLE_SYNC_IRQ_GPIO -- To view, visit https://review.coreboot.org/c/coreboot/+/78137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d093d94a666263684645ef724e945069c68c806 Gerrit-Change-Number: 78137 Gerrit-PatchSet: 5 Gerrit-Owner: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: drivers/intel/gma/opregion: Use CBFS cache to load VBT
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77886?usp=email ) Change subject: drivers/intel/gma/opregion: Use CBFS cache to load VBT ...................................................................... drivers/intel/gma/opregion: Use CBFS cache to load VBT Thanks to x86 CBFS cache support, we can leverage cbfs_map() function to load the VBT binary regardless of if it is compressed or not. Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77886 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/opregion.c M src/soc/intel/alderlake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/tigerlake/Kconfig 6 files changed, 25 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 47f7617..ca0143d 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -59,10 +59,6 @@ config INTEL_GMA_LIBGFXINIT_EDID bool -config VBT_DATA_SIZE_KB - int - default 8 - config VBT_CBFS_COMPRESSION_DEFAULT_LZ4 def_bool n help diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index fe333fa..d551638 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -19,40 +19,39 @@ return "vbt.bin"; } -static char vbt_data[CONFIG_VBT_DATA_SIZE_KB * KiB]; -static size_t vbt_data_sz; - void *locate_vbt(size_t *vbt_size) { - uint32_t vbtsig = 0; + static void *data; + static size_t size; - if (vbt_data_sz != 0) { - if (vbt_size) - *vbt_size = vbt_data_sz; - return (void *)vbt_data; + if (data) + goto out; + + data = cbfs_map(mainboard_vbt_filename(), &size); + if (!data || size == 0) { + printk(BIOS_ERR, "Could not find or load %s CBFS file\n", + mainboard_vbt_filename()); + goto err; } - const char *filename = mainboard_vbt_filename(); - - size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data)); - - if (file_size == 0) - return NULL; - - if (vbt_size) - *vbt_size = file_size; - - memcpy(&vbtsig, vbt_data, sizeof(vbtsig)); - if (vbtsig != VBT_SIGNATURE) { - printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n"); - return NULL; + if (*(uint32_t *)data == VBT_SIGNATURE) { + printk(BIOS_INFO, "Found a VBT of %zu bytes\n", size); + goto out; } - printk(BIOS_INFO, "Found a VBT of %zu bytes after decompression\n", - file_size); - vbt_data_sz = file_size; + printk(BIOS_ERR, "Missing/invalid signature in VBT data file!\n"); - return (void *)vbt_data; +err: + if (data) { + cbfs_unmap(data); + data = NULL; + } + size = 0; + +out: + if (vbt_size && size) + *vbt_size = size; + return data; } /* Write ASLS PCI register and prepare SWSCI register. */ diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 251695e..eea27fc 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -350,10 +350,6 @@ default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE -config VBT_DATA_SIZE_KB - int - default 9 - # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) # ADL UART source clock: 100MHz diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 3d84991..9f70177 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -174,10 +174,6 @@ hex default 0xc35 -config VBT_DATA_SIZE_KB - int - default 9 - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index d0db3e2..05d7f70 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -301,10 +301,6 @@ default 0xfe02c000 depends on INTEL_LPSS_UART_FOR_CONSOLE -config VBT_DATA_SIZE_KB - int - default 9 - # Clock divider parameters for 115200 baud rate # Baudrate = (UART source clock * M) /(N *16) # MTL UART source clock: 100MHz diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c07a0d8..2d5cf08 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -222,10 +222,6 @@ hex default 0x7fff -config VBT_DATA_SIZE_KB - int - default 9 - config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/77886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e37e718a71bd85b0d7dee1efc4c0391798f16f7 Gerrit-Change-Number: 77886 Gerrit-PatchSet: 34 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: commonlib/fsp_relocate: Fix potential NULL pointer dereference
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78501?usp=email ) Change subject: commonlib/fsp_relocate: Fix potential NULL pointer dereference ...................................................................... commonlib/fsp_relocate: Fix potential NULL pointer dereference Commit 1df1cf994aa9 ("commonlib/fsp_relocate: add PE32 section support") introduced a potential NULL pointer dereference if there is PE32 binary to relocate outside of the first firmware volume. The `fih_offset' pointer was used as an output variable but now it is also used as an input variable to pass the FSP information header to the `pe_relocate()' function. This commit resolves this potential NULL-pointer dereference by passing the pointer systematically and without affecting the logic as it is only set if it has not been set before. Change-Id: I9fad90a60854d5f050aa044a5c0b3af91c99df4a Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78501 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/fsp_relocate.c 1 file changed, 3 insertions(+), 9 deletions(-) Approvals: Bora Guvendik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 379930b..96d31b3 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -584,7 +584,7 @@ printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset); /* First file and section should be FSP info header. */ - if (fih_offset != NULL && *fih_offset == 0) + if (*fih_offset == 0) *fih_offset = file_offset; ffsfh = relative_offset(fsp, file_offset); @@ -671,14 +671,8 @@ while (offset < size) { ssize_t nparsed; - /* Relocate each FV within the FSP region. The FSP_INFO_HEADER - * should only be located in the first FV. */ - if (offset == 0) - nparsed = relocate_fvh(new_addr, fsp, size, offset, - &fih_offset); - else - nparsed = relocate_fvh(new_addr, fsp, size, offset, - NULL); + /* Relocate each FV within the FSP region. */ + nparsed = relocate_fvh(new_addr, fsp, size, offset, &fih_offset); /* FV should be larger than 0 or failed to parse. */ if (nparsed <= 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/78501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9fad90a60854d5f050aa044a5c0b3af91c99df4a Gerrit-Change-Number: 78501 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Ed Sharma <aeddiesharma(a)fb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/*: Ensure PSP soft fuse bitmask set properly
by Felix Held (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78823?usp=email ) Change subject: soc/amd/*: Ensure PSP soft fuse bitmask set properly ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e207e20132d44016fbcb986bdfd8e935d8fead5 Gerrit-Change-Number: 78823 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 13:28:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/mendocino: Update FSP-S UPD to pass boot logo
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78817?usp=email ) Change subject: soc/amd/mendocino: Update FSP-S UPD to pass boot logo ...................................................................... soc/amd/mendocino: Update FSP-S UPD to pass boot logo A new FSP-S UPD is added to allow passing a buffer containing boot logo in BMP format. Update the FSP-S UPD and add a SoC specific callback to populate the UPD. BUG=b:294055390 TEST=Build and boot to OS in Skyrim. Pass the BMP logo buffer through the UPD to FSP-S. Ensure that the concerned driver in FSP-S handles the buffer. Change-Id: Ie522956b6dfe2400ef91d43c80f2adc6d52c8415 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78817 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/mendocino/fsp_s_params.c M src/vendorcode/amd/fsp/mendocino/FspsUpd.h 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index ce450e8..e1eff32 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -6,6 +6,7 @@ #include <amdblocks/apob_cache.h> #include <amdblocks/vbios_cache.h> #include <bootmode.h> +#include <bootsplash.h> #include <console/console.h> #include <device/pci.h> #include <fsp/api.h> @@ -52,3 +53,9 @@ if (!acpi_is_wakeup_s3()) payload_preload(); } + +void soc_load_logo(FSPS_UPD *supd) +{ + uint32_t logo_size; + bmp_load_logo(&supd->FspsConfig.logo_bmp_buffer, &logo_size); +} diff --git a/src/vendorcode/amd/fsp/mendocino/FspsUpd.h b/src/vendorcode/amd/fsp/mendocino/FspsUpd.h index 3ac52c0..fd250d1 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspsUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspsUpd.h @@ -11,7 +11,8 @@ typedef struct __packed { /** Offset 0x0020**/ uint32_t vbios_buffer; - /** Offset 0x0024**/ uint64_t gop_reserved; + /** Offset 0x0024**/ uint32_t gop_reserved; + /** Offset 0x0028**/ uint32_t logo_bmp_buffer; /** Offset 0x002C**/ uint32_t reserved1; /** Offset 0x0030**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/78817?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie522956b6dfe2400ef91d43c80f2adc6d52c8415 Gerrit-Change-Number: 78817 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/amd/common/psp: Remove unnecessary prompts from Kconfig
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78818?usp=email ) Change subject: soc/amd/common/psp: Remove unnecessary prompts from Kconfig ...................................................................... soc/amd/common/psp: Remove unnecessary prompts from Kconfig I think this was probably a cut & paste error. We don't want prompts for the "default" Kconfig options. Those should be set by the platform, not the end user. These prompts didn't make sense where they were in the Kconfig menus either. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Idcd2ba84591d31a9a25bcc6cae3ec163939d7836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78818 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/amd/common/block/psp/Kconfig 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Eric Lai: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index d86ad7c..47e3fc4 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -94,25 +94,25 @@ Select this config to indicate SoC includes Hardware Security Processor(HSP). config AMD_FWM_POSITION_20000_DEFAULT - bool "0x20000" + bool config AMD_FWM_POSITION_420000_DEFAULT - bool "0x420000" + bool config AMD_FWM_POSITION_820000_DEFAULT - bool "0x820000" + bool config AMD_FWM_POSITION_C20000_DEFAULT - bool "0xC20000" + bool config AMD_FWM_POSITION_E20000_DEFAULT - bool "0xE20000" + bool config AMD_FWM_POSITION_F20000_DEFAULT - bool "0xF20000" + bool config AMD_FWM_POSITION_FA0000_DEFAULT - bool "0xFA0000" + bool choice AMD_FWM_POSITION_CHOICE prompt "AMD FW position" -- To view, visit https://review.coreboot.org/c/coreboot/+/78818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcd2ba84591d31a9a25bcc6cae3ec163939d7836 Gerrit-Change-Number: 78818 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/*: Correct ACPI device name for eMMC
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78825?usp=email ) Change subject: soc/intel/*: Correct ACPI device name for eMMC ...................................................................... soc/intel/*: Correct ACPI device name for eMMC The ACPI name of any device needs to match the name used for generating the S0i3 LPI constraint list, which comes from soc_acpi_name() for each SoC. The names used for the eMMC controller do not match, which will lead to broken ACPI tables since the LPI constriant will reference an ACPI device which does not exist. Some OSes tolerate this better than others, but it should still be corrected. TEST=build/boot google/{hatch,volteer, brya}, dump ACPI and verify no invalid device names referenced. Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78825 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/intel/alderlake/acpi/scs.asl M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/elkhartlake/acpi/scs.asl M src/soc/intel/jasperlake/acpi/scs.asl 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/alderlake/acpi/scs.asl b/src/soc/intel/alderlake/acpi/scs.asl index aac78e8..d39c66d 100644 --- a/src/soc/intel/alderlake/acpi/scs.asl +++ b/src/soc/intel/alderlake/acpi/scs.asl @@ -18,7 +18,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name(TEMP, 0) diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 7def761..fcadcbd 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -15,7 +15,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) diff --git a/src/soc/intel/elkhartlake/acpi/scs.asl b/src/soc/intel/elkhartlake/acpi/scs.asl index c6d71c1..3955402 100644 --- a/src/soc/intel/elkhartlake/acpi/scs.asl +++ b/src/soc/intel/elkhartlake/acpi/scs.asl @@ -15,7 +15,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index b58608f..491df51 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -15,7 +15,7 @@ } /* EMMC */ - Device(PEMC) { + Device(EMMC) { Name(_ADR, 0x001A0000) Name (_DDN, "eMMC Controller") Name (TEMP, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/78825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbc22b6b2a84bbe73f1b09083f27081612db5eba Gerrit-Change-Number: 78825 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: Use common GCD function
by Eric Lai (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Arthur Heymans, Julius Werner, Yidi Lin. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78799?usp=email ) Change subject: Use common GCD function ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Gerrit-Change-Number: 78799 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 13:23:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2023