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Change subject: arch/arm64/arch_timer: Fix possible overflow in multiplication
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
> @jwerner, Herobrine's bootblock excceeds allocated size(40K). […]
Can you take a look at the space usage for each symbol (iirc it's already under somewhere in the build folder), and see if there's anything that can be reduced (such as a table)?
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Change subject: Use common GCD function
......................................................................
Patch Set 6: Code-Review+2
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Change subject: Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
......................................................................
Patch Set 15: Code-Review+1
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Change subject: 3rdparty/libgfxinit: Update submodule to upstream main
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
These commits won't do anything without the rest of the TGL/ADL bringup,
which will still take some time.
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Change subject: acpi/acpi.h: Add IO Remapping Table structures
......................................................................
Patch Set 3:
(2 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/77884/comment/6fea6d92_a0b4e0a8 :
PS3, Line 9: Table(IORT)
> Please add a space before the (.
Done
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/77884/comment/8c88c45e_ccd7c164 :
PS3, Line 1205: /* (Re)calculate length. */
> No dot/period at the end needed.
Done
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Hello Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/78827?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+1 by Paul Menzel
Change subject: sb/intel/bd82x6x/early_usb: Print error for invalid USB setting
......................................................................
sb/intel/bd82x6x/early_usb: Print error for invalid USB setting
According to BWG the USB current setting 0 should not be used for desktop
boards. As autoport defaults to 0 if the USB current doesn't match one of
the lookup table entries most of the desktop boards in tree have a such
setting. Print an error to alert users of such boards to update the USB
current settings.
Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/southbridge/intel/bd82x6x/early_usb.c
1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/78827/6
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Change subject: arch/arm64/arch_timer: Fix possible overflow in multiplication
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
@jwerner, Herobrine's bootblock excceeds allocated size(40K).
Do you have any suggestion to fix this ?
https://qa.coreboot.org/job/coreboot-gerrit/247611/testReport/junit/(root)/…
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Change subject: Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
......................................................................
Patch Set 15: Code-Review+1
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Change subject: Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
......................................................................
Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
Commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large
value") breaks S3 resume from TSEG stage cache on many platforms,
including GM45 and Ivy Bridge, so limit it to 512 KiB.
HEAP_SIZE overrides greater than 512K prior to the commit above are
restored.
Please test this against other platforms before merging!
Tested: Setting it to 0x80000 results a working S3 resume on Thinkpad
X200 and T430, with log in cbmem for S3 resume, while 0xa0000
breaks it. coreboot log during failed resume when (HEAP_SIZE
>= 0xa0000) cannot be obtained from EHCI debug, while log in
cbmem shows that ramstage is failed to be found in TSEG stage
cache, as shown in https://ticket.coreboot.org/issues/512 .
Resolves: https://ticket.coreboot.org/issues/512
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: Ib1de1eb8487df5bdf004e544d40667833a291515
---
M src/Kconfig
M src/northbridge/amd/pi/Kconfig
M src/soc/amd/picasso/Kconfig
M src/soc/amd/stoneyridge/Kconfig
4 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/78623/15
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Change subject: Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
......................................................................
Kconfig: Decrease default HEAP_SIZE from 1 MiB to 512 KiB
Commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large
value") breaks S3 resume from TSEG stage cache on many platforms,
including GM45 and Ivy Bridge, so limit it to 512 KiB.
Please test this against other platforms before merging!
Tested: Setting it to 0x80000 results a working S3 resume on Thinkpad
X200 and T430, with log in cbmem for S3 resume, while 0xa0000
breaks it. coreboot log during failed resume when (HEAP_SIZE
>= 0xa0000) cannot be obtained from EHCI debug, while log in
cbmem shows that ramstage is failed to be found in TSEG stage
cache, as shown in https://ticket.coreboot.org/issues/512 .
Resolves: https://ticket.coreboot.org/issues/512
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: Ib1de1eb8487df5bdf004e544d40667833a291515
---
M src/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/78623/14
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