coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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3036 discussions

[XS] Change in coreboot[master]: mb/google/dedede/var/pirika: Support for CXMT CXDB4CBAM-ML-A
by Karthik Ramasubramanian (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Anson Tseng, Daniel Peng, Shou-Chieh Hsu, Subrata Banik. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78792?usp=email ) Change subject: mb/google/dedede/var/pirika: Support for CXMT CXDB4CBAM-ML-A ...................................................................... Patch Set 2: (1 comment) File spd/lp4x/set-1/parts_spd_manifest.generated.txt: https://review.coreboot.org/c/coreboot/+/78792/comment/251d217a_9023b041 : PS2, Line 36: CXDB4CBAM-ML-A,spd-11.hex > should't this be a separate CL ? +1. This should be a separate CL. Also where is the update to memory_parts.json file describing the memory characteristics for this part. -- To view, visit https://review.coreboot.org/c/coreboot/+/78792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Gerrit-Change-Number: 78792 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:03:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Jérémy Compostella (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Eugene Myers, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78889?usp=email ) Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 4 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:01:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Eugene Myers (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Jérémy Compostella, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Eugene Myers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78889?usp=email ) Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... Patch Set 4: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78889/comment/cfdd58d6_9f21364e : PS1, Line 9: When the STM is configured, get_save_state returns an incorrect > nit: This is more of my rule as I don't think I saw that in coreboot coding style but I usually feel […] Done Patchset: PS4: I opted not to change the code (the suggestion actually contained a bug should be "size -= ALIGN...") - I would still have to test it to make sure. File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/78889/comment/43c56985_7f2973d7 : PS1, Line 12: #include <security/intel/stm/SmmStm.h> > includes are usually sorted in alphabetical order. Done https://review.coreboot.org/c/coreboot/+/78889/comment/6b6c1b5c_b67d5729 : PS1, Line 104: size_t stm_psd_size = 0; > ``` […] Acknowledged https://review.coreboot.org/c/coreboot/+/78889/comment/80f7ec82_08ac75c2 : PS1, Line 111: 0x100); > It should fit on one line. The coding style states 96 columns. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 4 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 19:47:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: Revert "util/crossgcc: Update gcc to 11.2"
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Mike Banon. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636?usp=email ) Change subject: Revert "util/crossgcc: Update gcc to 11.2" ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Mike, we'd like to move these commits to the abandoned state. I understand how you're using them, but they show up as conflicts to other patches and in lists of changes when we're looking at what needs to be merged in various directories. Feel free to bring them back to rebase them when needed, but if you wouldn't mind keeping them in an abandoned state for the rest of the time, it'd be appreciated. I've removed the reviewers so this won't show up on their todo lists as well. Thanks. Martin -- To view, visit https://review.coreboot.org/c/coreboot/+/59636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09a789f9ccb284ac7cad32b12bbf60ecb82efb44 Gerrit-Change-Number: 59636 Gerrit-PatchSet: 3 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 19:39:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Eugene Myers (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Eugene Myers, Martin L Roth, Michał Żygowski, Paul Menzel, Stefan Reinauer. Hello EliasOfWaffle, Jérémy Compostella, Martin L Roth, Matt DeVillier, Michał Żygowski, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78889?usp=email to look at the new patch set (#3). Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... cpu/x86/smm: Fix get_save_state calculation When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100)of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. This patch addresses the issue identified in CB:76601, which means that SMMSTOREv2 now works with the STM. Resolves: https://ticket.coreboot.org/issues/511 Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Signed-off-by: Eugene D. Myers <edmyers(a)cyberpackventures.com> --- M src/cpu/x86/smm/smm_module_handler.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/78889/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
by Paul Menzel (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Daniel Peng, Karthik Ramasubramanian, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78310?usp=email ) Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/78310/comment/400a8fa8_fa77c9c0 : PS3, Line 8: Please motivate the change, by stating the problem. Maybe: In contrast to the MediaTek MT7921L, the Intel AX211NGW needs to load a SAR table. So, add … -- To view, visit https://review.coreboot.org/c/coreboot/+/78310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Gerrit-Change-Number: 78310 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 19:36:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/arm64/cache: Add cache_numsets and cache_line_bytes
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78062?usp=email ) Change subject: arch/arm64/cache: Add cache_numsets and cache_line_bytes ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/78062?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec6e7e66a12ca6acb4a1f2158866bc91aa3f7e25 Gerrit-Change-Number: 78062 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[main]: arch/arm64/cache: Add cache_numsets and cache_line_bytes
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78846?usp=email ) Change subject: arch/arm64/cache: Add cache_numsets and cache_line_bytes ...................................................................... arch/arm64/cache: Add cache_numsets and cache_line_bytes Add two more helper functions for the ARM64 cache: - cache_numsets to retrieve the number of sets in a cache - cache_line_bytes to retrieve the number of bytes per cache line Background: We need those functions for a mainboard we are currently working on. Change-Id: Iec6e7e66a12ca6acb4a1f2158866bc91aa3f7e25 Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> --- M src/arch/arm64/armv8/cache.c M src/arch/arm64/include/armv8/arch/cache.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/78846/1 diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index dbaedec..2382ddf 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -86,6 +86,20 @@ return line_bytes; } +uint64_t cache_numsets(const enum cache_level level, const enum cache_type type) +{ + /* select cache...and read back its ID register afterwards */ + raw_write_csselr_el1(((level - 1) << 1) | (type == CACHE_INSTRUCTION)); + return get_ccsidr_el1_numsets( raw_read_ccsidr_el1() ) + 1; +} + +uint8_t cache_line_bytes(const enum cache_level level, const enum cache_type type) +{ + /* select cache...and read back its ID register afterwards */ + raw_write_csselr_el1(((level - 1) << 1) | (type == CACHE_INSTRUCTION)); + return (1 << ((raw_read_ccsidr_el1() & 0x7) + 4)); +} + enum dcache_op { OP_DCCSW, OP_DCCISW, diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 3a72d40..9b0ef32 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -51,6 +51,12 @@ /* returns number of bytes per cache line */ unsigned int dcache_line_bytes(void); +/* returns number of sets in the specified cache */ +uint64_t cache_numsets(const enum cache_level level, const enum cache_type type); + +/* returns number of bytes per cache line of the specified cache */ +uint8_t cache_line_bytes(const enum cache_level level, const enum cache_type type); + /* Invalidate all TLB entries. */ static inline void tlb_invalidate_all(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/78846?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec6e7e66a12ca6acb4a1f2158866bc91aa3f7e25 Gerrit-Change-Number: 78846 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
by Paul Menzel (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Daniel Peng, Karthik Ramasubramanian, Nick Vaccaro. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78310?usp=email ) Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78310/comment/d5f61a2a_6b355e21 : PS3, Line 2: Daniel_Peng Please update your git configuration to remove the underscore in the name: $ git config --global user.name "Daniel Peng" $ git commit -s --amend --author="Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>" File src/mainboard/google/brya/variants/marasov/variant.c: https://review.coreboot.org/c/coreboot/+/78310/comment/564388d9_d969f420 : PS3, Line 13: printk(BIOS_INFO, "Use wifi_sar_1.hex.\n"); Info messages should be understandable to “normal” users. Could you please rephrase it? https://review.coreboot.org/c/coreboot/+/78310/comment/7ca7a320_92138d44 : PS3, Line 17: printk(BIOS_INFO, "Intel Wi-Fi SAR not used, return NULL!\n"); It’d be great, if you rephrased this too. -- To view, visit https://review.coreboot.org/c/coreboot/+/78310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Gerrit-Change-Number: 78310 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 19:32:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/arm64/cache: Implement helpers to obtain CPU cache details
by Martin L Roth (Code Review) 02 Nov '23

02 Nov '23

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/78061?usp=email ) Change subject: arch/arm64/cache: Implement helpers to obtain CPU cache details ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/78061?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7022fc3c0035208bc3fdc716fc33f6b78d8e74fc Gerrit-Change-Number: 78061 Gerrit-PatchSet: 1 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit November 2023