coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: [TEST ONLY] add VPRO features control by fw config
by Wonkyu Kim (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75714?usp=email to look at the new patch set (#3). Change subject: [TEST ONLY] add VPRO features control by fw config ...................................................................... [TEST ONLY] add VPRO features control by fw config Define keylocker, tme fw_config bits(24-25) field KEYLOCKER 24 option KEYLOCKER_EN 0 option KEYLOCKER_DIS 1 end field TME 25 option TME_EN 0 option TME_DIS 1 end Vpro features Disable: 3XXXXXX (XXXXXX is existing fw_config value) Vpro features Enable : XXXXXX (XXXXXX is existing fw_config value) ex)proto1 SKU1 fw_config: 0x1561 0x1561 => Vpro features(keylocker/tme) are enabled 0x3001561 => Vpro features(keylocker/tme) are disabled localhost ~ # cbmem -c | grep fw_config ... [DEBUG] keylocker is disabled by fw_config ... [DEBUG] TME is disabled by fw config How to read FW config From EC console, type "cbi" to read FW config ex) 23-05-17 23:33:33.229 ec:~$ cbi ... 23-05-17 23:41:33.248 FW_CONFIG: 5473 (0x1561) ... How to write FW config From EC consone, type "cbi set 6 <FW config value> 4 ex) 23-05-17 23:43:42.320 ec:~$ cbi set 6 0x3001561 4 Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I746ba80279dc69d06ac9e06bfeae068e31d23694 --- M src/cpu/intel/common/common_init.c M src/mainboard/google/rex/variants/rex0/Makefile.inc A src/mainboard/google/rex/variants/rex0/cpulib.c M src/mainboard/google/rex/variants/rex0/overridetree.cb M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 6 files changed, 74 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/75714/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I746ba80279dc69d06ac9e06bfeae068e31d23694 Gerrit-Change-Number: 75714 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: doc/soc/intel/xeon_sp: Add Xeon Scalable processor coreboot community...
by David Hendricks (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Anjaneya "Reddy" Chagam, Felix Singer, Jonathan Zhang, Shuo Liu. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78787?usp=email ) Change subject: doc/soc/intel/xeon_sp: Add Xeon Scalable processor coreboot community preview guide ...................................................................... Patch Set 5: Code-Review-1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78787/comment/3610b9f8_352ddb61 : PS5, Line 7: Xeon Scalable processor coreboot Xeon-SP https://review.coreboot.org/c/coreboot/+/78787/comment/f5bae96e_7ca75539 : PS5, Line 10: Put a ':' here and the URL on the line below. Patchset: PS5: Thanks a lot for writing this up! It looks good to me, except for some line length issues. File Documentation/soc/intel/xeon_sp/community_preview_guide.md: https://review.coreboot.org/c/coreboot/+/78787/comment/e175832d_edf9e72a : PS5, Line 9: For Granite Rapids coreboot, we are going to perform a phased upstreaming strategy according to the maturity of the code. : A community preview branch is opensource at https://review.coreboot.org/plugins/gitiles/intel-dev-pub/. : : The community preview branch initially contains codes on legacy feature enabling and matured patch set for platform support. : More platform support code will come with the platform development. The subsequent upstreaming work will be based on : this branch. It provides 2 board targets, Please break these (and other) long lines to fit within 96 columns [1]. Typically we try to keep within the coding style parameters for documentation, although there is an exception for URLs or tables that would don't render properly if broken. [1] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/Docu… -- To view, visit https://review.coreboot.org/c/coreboot/+/78787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2ffc1722a4a26d6039b6642efa95bf072d896ad Gerrit-Change-Number: 78787 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 22:14:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/alderlake: Add missing min sleep state for DPTF device
by Felix Singer (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Matt DeVillier, Nick Vaccaro. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78877?usp=email ) Change subject: soc/intel/alderlake: Add missing min sleep state for DPTF device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Gerrit-Change-Number: 78877 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 02 Nov 2023 21:50:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Eugene Myers (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Jérémy Compostella, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Eugene Myers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78889?usp=email ) Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... Patch Set 5: (2 comments) Patchset: PS5: This should work and actually a simpler solution. From what I can see, it is equivalent File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/78889/comment/bbac5873_04076f55 : PS4, Line 110: stm_psd_size = ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), > I am talking about a huge change. Just sharing definition. Here is what I have in mind. > > ``` > Author: Jeremy Compostella <jeremy.compostella(a)intel.com> > AuthorDate: Thu Nov 2 13:55:24 2023 -0700 > Commit: Jeremy Compostella <jeremy.compostella(a)intel.com> > CommitDate: Thu Nov 2 13:59:04 2023 -0700 > > cpu/x86/smm: Define STM descriptor size in SMM save state > > Change-Id: Id68f9e650be24dd4d96788d2eeaea3dd88c26bd3 > Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> > > 3 files changed, 11 insertions(+), 12 deletions(-) > src/cpu/x86/mp_init.c | 5 +---- > src/cpu/x86/smm/smm_module_handler.c | 9 +-------- > src/include/cpu/x86/smm.h | 9 +++++++++ > > modified src/cpu/x86/mp_init.c > @@ -1087,10 +1087,7 @@ static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops) > /* > * Make sure there is enough room for the SMM descriptor > */ > - if (CONFIG(STM)) { > - state->smm_save_state_size += > - ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100); > - } > + state->smm_save_state_size += STM_PSD_SIZE; > > /* > * Default to smm_initiate_relocation() if trigger callback isn't > modified src/cpu/x86/smm/smm_module_handler.c > @@ -101,18 +101,11 @@ struct global_nvs *gnvs; > > void *smm_get_save_state(int cpu) > { > - size_t stm_psd_size = 0; > - > if (cpu > smm_runtime.num_cpus) > return NULL; > > - if (CONFIG(STM)) { > - stm_psd_size = ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), > - 0x100); > - } > - > return (void *)(smm_runtime.save_state_top[cpu] - > - (smm_runtime.save_state_size - stm_psd_size)); > + (smm_runtime.save_state_size - STM_PSD_SIZE)); > } > > uint32_t smm_revision(void) > modified src/include/cpu/x86/smm.h > @@ -33,6 +33,15 @@ > > #define SMM_PCI_RESOURCE_STORE_NUM_RESOURCES 6 > > +/* > + * SMI Transfer Monitor (STM) descriptor reserved in SMM save state. > + */ > +#if CONFIG(STM) > +#define STM_PSD_SIZE ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100) > +#else > +#define STM_PSD_SIZE 0 > +#endif > + > /* Send cmd to APM_CNT with HAVE_SMI_HANDLER checking. */ > int apm_control(u8 cmd); > u8 apm_get_apmc(void); > > ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 5 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 21:21:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORT
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Karthik Ramasubramanian. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78882?usp=email ) Change subject: soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORT ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6112c03723dcbc34cb0f57c400f831c765b95115 Gerrit-Change-Number: 78882 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 02 Nov 2023 21:14:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORT
by Karthik Ramasubramanian (Code Review) 02 Nov '23

02 Nov '23

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78882?usp=email ) Change subject: soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORT ...................................................................... soc/amd/mendocino: Conditionally select HAVE_FSP_LOGO_SUPPORT Indicate FSP has support to display logo when graphics initialization is done in FSP. BUG=b:294055390 TEST=Build and boot to OS in Skyrim with and without passing the BMP logo buffer from coreboot. Change-Id: I6112c03723dcbc34cb0f57c400f831c765b95115 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/mendocino/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/78882/1 diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 2fcd508..ef72280 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -17,6 +17,7 @@ select HAVE_CF9_RESET select HAVE_EM100_SUPPORT select HAVE_FSP_GOP + select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select PARALLEL_MP_AP_WORK -- To view, visit https://review.coreboot.org/c/coreboot/+/78882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6112c03723dcbc34cb0f57c400f831c765b95115 Gerrit-Change-Number: 78882 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: pc80/rtc: Clear CMOS on errors on S3 resume too
by Jérémy Compostella (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Bill XIE, Kyösti Mälkki, Nico Huber. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78881?usp=email ) Change subject: pc80/rtc: Clear CMOS on errors on S3 resume too ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/78881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1533875466f6eb7b409bb19ef98f6dcaf2d115c4 Gerrit-Change-Number: 78881 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 21:05:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Jérémy Compostella (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Eugene Myers, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78889?usp=email ) Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... Patch Set 5: (1 comment) File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/78889/comment/5e6256ba_9e837db9 : PS4, Line 110: stm_psd_size = ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), > The inconsistency is in the definition of smm_runtime. […] I am talking about a huge change. Just sharing definition. Here is what I have in mind. ``` Author: Jeremy Compostella <jeremy.compostella(a)intel.com> AuthorDate: Thu Nov 2 13:55:24 2023 -0700 Commit: Jeremy Compostella <jeremy.compostella(a)intel.com> CommitDate: Thu Nov 2 13:59:04 2023 -0700 cpu/x86/smm: Define STM descriptor size in SMM save state Change-Id: Id68f9e650be24dd4d96788d2eeaea3dd88c26bd3 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> 3 files changed, 11 insertions(+), 12 deletions(-) src/cpu/x86/mp_init.c | 5 +---- src/cpu/x86/smm/smm_module_handler.c | 9 +-------- src/include/cpu/x86/smm.h | 9 +++++++++ modified src/cpu/x86/mp_init.c @@ -1087,10 +1087,7 @@ static void fill_mp_state_smm(struct mp_state *state, const struct mp_ops *ops) /* * Make sure there is enough room for the SMM descriptor */ - if (CONFIG(STM)) { - state->smm_save_state_size += - ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100); - } + state->smm_save_state_size += STM_PSD_SIZE; /* * Default to smm_initiate_relocation() if trigger callback isn't modified src/cpu/x86/smm/smm_module_handler.c @@ -101,18 +101,11 @@ struct global_nvs *gnvs; void *smm_get_save_state(int cpu) { - size_t stm_psd_size = 0; - if (cpu > smm_runtime.num_cpus) return NULL; - if (CONFIG(STM)) { - stm_psd_size = ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), - 0x100); - } - return (void *)(smm_runtime.save_state_top[cpu] - - (smm_runtime.save_state_size - stm_psd_size)); + (smm_runtime.save_state_size - STM_PSD_SIZE)); } uint32_t smm_revision(void) modified src/include/cpu/x86/smm.h @@ -33,6 +33,15 @@ #define SMM_PCI_RESOURCE_STORE_NUM_RESOURCES 6 +/* + * SMI Transfer Monitor (STM) descriptor reserved in SMM save state. + */ +#if CONFIG(STM) +#define STM_PSD_SIZE ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100) +#else +#define STM_PSD_SIZE 0 +#endif + /* Send cmd to APM_CNT with HAVE_SMI_HANDLER checking. */ int apm_control(u8 cmd); u8 apm_get_apmc(void); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 5 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 21:02:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eugene Myers <cedarhouse1(a)comcast.net> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: pc80/rtc: Clear CMOS on errors on S3 resume too
by Jonathon Hall (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Bill XIE, Jérémy Compostella, Kyösti Mälkki, Nico Huber. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78881?usp=email ) Change subject: pc80/rtc: Clear CMOS on errors on S3 resume too ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1533875466f6eb7b409bb19ef98f6dcaf2d115c4 Gerrit-Change-Number: 78881 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:54:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: pc80/rtc: Clear CMOS on errors on S3 resume too
by Nico Huber (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Bill XIE, Jonathon Hall, Kyösti Mälkki. Hello Bill XIE, Jonathon Hall, Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/78881?usp=email to review the following change. Change subject: pc80/rtc: Clear CMOS on errors on S3 resume too ...................................................................... pc80/rtc: Clear CMOS on errors on S3 resume too Commit 29030d0f3dad (drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume) meant to fix an issue with the static option table. However, it also disabled CMOS clearing on errors for the S3 resume path. As we'd still want to clear CMOS when its contents are corrupted, reduce the S3 exception to the static-option-table case. Change-Id: I1533875466f6eb7b409bb19ef98f6dcaf2d115c4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/pc80/rtc/option.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/78881/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 0954335..d2b3de2 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -201,8 +201,8 @@ { const unsigned char *cmos_default; const bool cmos_need_reset = - (CONFIG(STATIC_OPTION_TABLE) || cmos_error() || !cmos_lb_cks_valid()) - && !acpi_is_wakeup_s3(); + (CONFIG(STATIC_OPTION_TABLE) && !acpi_is_wakeup_s3()) + || cmos_error() || !cmos_lb_cks_valid(); size_t length = 128; size_t i; -- To view, visit https://review.coreboot.org/c/coreboot/+/78881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1533875466f6eb7b409bb19ef98f6dcaf2d115c4 Gerrit-Change-Number: 78881 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2023