coreboot-gerrit November 2023

coreboot-gerrit@coreboot.org

1 participants
3036 discussions

[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
by Jonathon Hall (Code Review) 02 Nov '23

02 Nov '23

Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78288?usp=email ) Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume ...................................................................... Patch Set 8: (1 comment) Patchset: PS4: > Interesting. If I understand correctly, this EC BRAM is more than a scratchpad […] Yes, that's right. Agree on refining restore that way too, I hope to give it a try but with a long TODO list and the immediate need solved by this change I have not had a chance yet. I'd be happy to review any patch if someone has the bandwidth to put it together. -- To view, visit https://review.coreboot.org/c/coreboot/+/78288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Gerrit-Change-Number: 78288 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:30:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Add missing min sleep state for DPTF device
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78877?usp=email ) Change subject: soc/intel/alderlake: Add missing min sleep state for DPTF device ...................................................................... soc/intel/alderlake: Add missing min sleep state for DPTF device Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:04.0 TEST=build/boot google/brya (banshee), verify warning not present in cbmem log, verify entry for DPTF device in ACPI LPI constraint list. Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/78877/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1dc14be7..7687f02 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -166,6 +166,7 @@ { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, + { SA_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/78877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90 Gerrit-Change-Number: 78877 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/poppy/var/nami: Fix SMBIOS name for Akali360
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78876?usp=email ) Change subject: mb/google/poppy/var/nami: Fix SMBIOS name for Akali360 ...................................................................... mb/google/poppy/var/nami: Fix SMBIOS name for Akali360 Remove space to improve compatibility with OS drivers and various tools, and to be consistent with other device names with the 360 suffix. TEST=build/boot Windows/Linux on Akali360, verify audio functional. Change-Id: Ib9b909dba939f726e6fbe71f5b4956b432086029 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/poppy/variants/nami/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/78876/1 diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index e764523..aaa51dd 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -197,7 +197,7 @@ snprintf(product, sizeof(product), "Akali"); break; case SKU_0_AKALI360: case SKU_1_AKALI360: - snprintf(product, sizeof(product), "Akali 360"); break; + snprintf(product, sizeof(product), "Akali360"); break; case SKU_0_BARD: case SKU_1_BARD: case SKU_2_BARD: -- To view, visit https://review.coreboot.org/c/coreboot/+/78876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9b909dba939f726e6fbe71f5b4956b432086029 Gerrit-Change-Number: 78876 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Eugene Myers (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Jérémy Compostella, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Eugene Myers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78889?usp=email ) Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78889/comment/d8cea46a_c0ccf3f0 : PS4, Line 9: When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100)of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. > missing space after the parenthesis. Done File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/78889/comment/ec7a50d8_86cb0a49 : PS4, Line 110: stm_psd_size = ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), > `ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100)` is also used in `src/cpu/x86/mp_init. […] The inconsistency is in the definition of smm_runtime.save_state_size, which was assumed to be the cpu save state (defined for the processor) and used in the tiling calculation for SMM. The STM's SMM descriptors had to also be accounted for when the STM is configured. I agree that someone may want to give more thought about how these data structures are dealt with. Not sure if I am the one to do it as I am trying to fix a serious bug. -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 5 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:25:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
by Nico Huber (Code Review) 02 Nov '23

02 Nov '23

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78288?usp=email ) Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume ...................................................................... Patch Set 8: (1 comment) Patchset: PS4: > I can't speak to the original purpose, but I use it currently to offer SeaBIOS ROMs for Mini v1/v2 t […] Interesting. If I understand correctly, this EC BRAM is more than a scratchpad and actually used to configure the EC firmware, correct? Reminds me that we also have payloads that read CMOS settings. So that's about the same situation: If we'd not write CMOS but only back get_option() with a file, those payloads wouldn't know about the static settings. I like the idea to only restore things that are covered by the option table. But for now I guess we won't need it. -- To view, visit https://review.coreboot.org/c/coreboot/+/78288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I533e83f3b95f327b0e24f4d750f8812325b7770b Gerrit-Change-Number: 78288 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:25:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing min sleep state for thermal device
by Matt DeVillier (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Matt DeVillier. Hello Eric Lai, Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78868?usp=email to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Add missing min sleep state for thermal device ...................................................................... soc/intel/cannonlake: Add missing min sleep state for thermal device Add an entry in the min_pci_sleep_states array for SA_DEVFN_THERMAL, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:12.0 TEST=build/boot google/puff (wyvern), verify warning not present in cbmem log, verify entry for THRM device in ACPI LPI constraint list. Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/78868/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Gerrit-Change-Number: 78868 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
by Subrata Banik (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Daniel Peng, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78310?usp=email ) Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module ...................................................................... Patch Set 3: -Code-Review (1 comment) Patchset: PS3: my bad, i just overlooked it -- To view, visit https://review.coreboot.org/c/coreboot/+/78310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Gerrit-Change-Number: 78310 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:10:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Eugene Myers (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Eugene Myers, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Hello EliasOfWaffle, Jérémy Compostella, Martin L Roth, Matt DeVillier, Michał Żygowski, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78889?usp=email to look at the new patch set (#5). Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... cpu/x86/smm: Fix get_save_state calculation When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100) of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. This patch addresses the issue identified in CB:76601, which means that SMMSTOREv2 now works with the STM. Resolves: https://ticket.coreboot.org/issues/511 Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Signed-off-by: Eugene D. Myers <edmyers(a)cyberpackventures.com> --- M src/cpu/x86/smm/smm_module_handler.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/78889/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 5 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[main]: cpu/x86/smm: Fix get_save_state calculation
by Jérémy Compostella (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: EliasOfWaffle, Eugene Myers, Martin L Roth, Matt DeVillier, Michał Żygowski, Paul Menzel, Stefan Reinauer. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78889?usp=email ) Change subject: cpu/x86/smm: Fix get_save_state calculation ...................................................................... Patch Set 4: -Code-Review (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/78889/comment/e3828b24_52706035 : PS4, Line 9: When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100)of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. missing space after the parenthesis. File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/78889/comment/b76e82f9_19342259 : PS4, Line 110: stm_psd_size = ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), `ALIGN_UP(sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR), 0x100)` is also used in `src/cpu/x86/mp_init.c::fill_mp_state_smm()`. Isn't time to define a macro, a shared function or whatever in order to prevent an inconsistency ? -- To view, visit https://review.coreboot.org/c/coreboot/+/78889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Gerrit-Change-Number: 78889 Gerrit-PatchSet: 4 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EliasOfWaffle <eliascontato(a)protonmail.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:07:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/brya/var/marasov: Enable wifi sar table for Intel module
by Karthik Ramasubramanian (Code Review) 02 Nov '23

02 Nov '23

Attention is currently required from: Daniel Peng, Nick Vaccaro. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78310?usp=email ) Change subject: mb/google/brya/var/marasov: Enable wifi sar table for Intel module ...................................................................... Patch Set 3: Code-Review-2 (1 comment) Patchset: PS3: Please move the change from master branch to main branch. This branch is not active anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/78310?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5c6bea6c2c916fb682044218ec7b3a5d2659f6 Gerrit-Change-Number: 78310 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 02 Nov 2023 20:06:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2023