coreboot-gerrit November 2023

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[XS] Change in coreboot[main]: payloads/LinuxBoot: Hide the path of the kernel and initrd when building
by Martin L Roth (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Arthur Heymans, Christian Walter, Stefan Reinauer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78651?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: payloads/LinuxBoot: Hide the path of the kernel and initrd when building ...................................................................... Patch Set 1: -Code-Review (1 comment) File payloads/external/LinuxBoot/Kconfig: https://review.coreboot.org/c/coreboot/+/78651/comment/785220d8_fcf65cd4 : PS1, Line 59: string "Path to kernel" if !LINUXBOOT_COMPILE_KERNEL I know I previously gave this a +2, but I've reconsidered. Let's change this to two lines, both here and below: ``` config LINUXBOOT_KERNEL_PATH string prompt "Path to kernel" if !LINUXBOOT_COMPILE_KERNEL ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/78651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7958e419e314a7018f84bf9c5c332c90f4a319df Gerrit-Change-Number: 78651 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 03 Nov 2023 15:42:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/braswell/Kconfig: Set HPET_MIN_TICKS
by Matt DeVillier (Code Review) 03 Nov '23

03 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78744?usp=email ) Change subject: soc/intel/braswell/Kconfig: Set HPET_MIN_TICKS ...................................................................... soc/intel/braswell/Kconfig: Set HPET_MIN_TICKS Commit 2bc9cee0f70f ("Braswell: Update the ACPI tables") switched the SoC from using its own HPET generation code to the common x86 code, but along the way the min_tick value got lost. Restore the original value prior to the above commit, which is now set via a Kconfig override. TEST=build/boot google/cyan (edgar), verify min_tick value in HPET ACPI table is correct. Change-Id: I2633e7cd0c3d74c1554ae8c1f2bb6387fd6dde2b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78744 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/braswell/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5aeb9e5..c3b93d2 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -115,6 +115,9 @@ Enable this to disable the HPET support Solves the Linux MP-BIOS bug timer not connected. +config HPET_MIN_TICKS + default 0x80 + config USE_GOOGLE_FSP bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/78744?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2633e7cd0c3d74c1554ae8c1f2bb6387fd6dde2b Gerrit-Change-Number: 78744 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/braswell: Unify DPTF enablement
by Matt DeVillier (Code Review) 03 Nov '23

03 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78743?usp=email ) Change subject: soc/intel/braswell: Unify DPTF enablement ...................................................................... soc/intel/braswell: Unify DPTF enablement Currently, there are 3 separate settings for DPTF which are not always in sync: - the enabled/disabled state of the devicetree PCI device - the 'dptf_enable' register, which sets the ACPI device status via GNVS - the 'DptfDisable' register, which sets the FSP UPD of the same name To make things sane, drop the two chip registers, and set the GNVS variable and FSP UPD based on the enabled/disabled status of the DPTF PCI device in the mainboard's devicetree. TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI devices are present/enabled when DPTF is enabled in devicetree, and not present/disabled when disabled in devicetree. Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/mainboard/facebook/fbg1701/devicetree.cb M src/mainboard/google/cyan/devicetree.cb M src/mainboard/intel/strago/devicetree.cb M src/mainboard/portwell/m107/devicetree.cb M src/mainboard/protectli/vault_bsw/devicetree.cb M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h 8 files changed, 4 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index a77a640..f0fd84b 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -62,7 +62,6 @@ register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect - register "DptfDisable" = "1" # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 5b7ef9a..9f510bf 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -77,8 +77,6 @@ # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - register "dptf_enable" = "true" - # Enable LPSS and LPE devices in ACPI mode register "lpss_acpi_mode" = "1" register "emmc_acpi_mode" = "0" @@ -97,7 +95,7 @@ device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 off end # 8086 22dc - Signal Processing Controller + device pci 0b.0 on end # 8086 22dc - PUNIT/DPTF device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port device pci 12.0 on end # 8086 0F16 - SD Port diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index d44a1b6..8701f90 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -66,8 +66,6 @@ # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock - register "dptf_enable" = "true" - # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" register "emmc_acpi_mode" = "1" @@ -86,7 +84,7 @@ device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - ? + device pci 0b.0 on end # 8086 22dc - PUNIT/DPTF device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port device pci 12.0 on end # 8086 0F16 - SD Port diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 3bc6737..8be3afa 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -62,7 +62,6 @@ register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect - register "DptfDisable" = "1" # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb index 02a1642..846722e 100644 --- a/src/mainboard/protectli/vault_bsw/devicetree.cb +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -62,7 +62,6 @@ register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect - register "DptfDisable" = "1" # Enable devices in PCI mode register "lpss_acpi_mode" = "0" diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index a278e55..718bfe9 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -70,9 +70,7 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { - const struct soc_intel_braswell_config *config = config_of_soc(); - - gnvs->dpte = config->dptf_enable; + gnvs->dpte = is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0)); /* Fill in the Wi-Fi Region ID */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index ce394d0..d3c41f8 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -79,7 +79,7 @@ params->AzaliaConfigPtr = 0; params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; params->ChvSvidConfig = config->ChvSvidConfig; - params->DptfDisable = config->DptfDisable; + params->DptfDisable = !is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0)); params->PcdEmmcMode = config->PcdEmmcMode; params->PcdUsb3ClkSsc = 1; params->PcdDispClkSsc = 1; diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 53627be..de86a12 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -42,8 +42,6 @@ struct soc_intel_braswell_config { bool enable_xdp_tap; - bool dptf_enable; - enum serirq_mode serirq_mode; /* Disable SLP_X stretching after SUS power well loss */ @@ -104,7 +102,6 @@ uint8_t PcdEnableI2C6; uint8_t PunitPwrConfigDisable; uint8_t ChvSvidConfig; - uint8_t DptfDisable; uint8_t PcdEmmcMode; uint8_t Usb2Port0PerPortPeTxiSet; uint8_t Usb2Port0PerPortTxiSet; -- To view, visit https://review.coreboot.org/c/coreboot/+/78743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Gerrit-Change-Number: 78743 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing entry to soc_acpi_name()
by Matt DeVillier (Code Review) 03 Nov '23

03 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78869?usp=email ) Change subject: soc/intel/cannonlake: Add missing entry to soc_acpi_name() ...................................................................... soc/intel/cannonlake: Add missing entry to soc_acpi_name() The device name for the SA thermal/DPTF PCI device was missing from soc_acpi_name(), leading to an invalid PLI device constraint entry being generated in the SSDT (the name field was blank/missing). Add the missing entry, matching the name to the existing ACPI device. TEST=build/boot Win11 on google/puff (wyvern) without a BSOD. Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78869 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 7d40634..2dc39b6 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -80,6 +80,7 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_IGD: return "GFX0"; + case SA_DEVFN_TS: return "TCPU"; case PCH_DEVFN_ISH: return "ISHB"; case SA_DEVFN_GNA: return "GNA"; case PCH_DEVFN_XHCI: return "XHCI"; -- To view, visit https://review.coreboot.org/c/coreboot/+/78869?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc Gerrit-Change-Number: 78869 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/cannonlake: Add missing min sleep state for thermal device
by Matt DeVillier (Code Review) 03 Nov '23

03 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78868?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/cannonlake: Add missing min sleep state for thermal device ...................................................................... soc/intel/cannonlake: Add missing min sleep state for thermal device Add an entry in the min_pci_sleep_states array for SA_DEVFN_THERMAL, to correct warning in cbmem log: [WARN] unknown min d_state for PCI device 00:12.0 TEST=build/boot google/puff (wyvern), verify warning not present in cbmem log, verify entry for THRM device in ACPI LPI constraint list. Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78868 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index ff93e2a..1545d19 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -170,6 +170,7 @@ { SA_DEVFN_TS, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, + { PCH_DEVFN_THERMAL, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_UFS, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_GSPI2, ACPI_DEVICE_SLEEP_D3 }, { PCH_DEVFN_ISH, ACPI_DEVICE_SLEEP_D3 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/78868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab Gerrit-Change-Number: 78868 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/puff/var/*: Set LAN/WLAN device type to generic
by Matt DeVillier (Code Review) 03 Nov '23

03 Nov '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78870?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/puff/var/*: Set LAN/WLAN device type to generic ...................................................................... mb/google/puff/var/*: Set LAN/WLAN device type to generic Change the LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices function correctly under Windows and Linux. Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/puff/variants/ambassador/overridetree.cb M src/mainboard/google/puff/variants/baseboard/devicetree.cb M src/mainboard/google/puff/variants/duffy/overridetree.cb M src/mainboard/google/puff/variants/faffy/overridetree.cb M src/mainboard/google/puff/variants/genesis/overridetree.cb M src/mainboard/google/puff/variants/kaisa/overridetree.cb M src/mainboard/google/puff/variants/moonbuggy/overridetree.cb M src/mainboard/google/puff/variants/noibat/overridetree.cb M src/mainboard/google/puff/variants/puff/overridetree.cb M src/mainboard/google/puff/variants/scout/overridetree.cb M src/mainboard/google/puff/variants/wyvern/overridetree.cb 11 files changed, 11 insertions(+), 11 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/puff/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb index 8b6a9ae..93e1c04 100644 --- a/src/mainboard/google/puff/variants/ambassador/overridetree.cb +++ b/src/mainboard/google/puff/variants/ambassador/overridetree.cb @@ -396,7 +396,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb index 6a32bdc..b7a9674 100644 --- a/src/mainboard/google/puff/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -323,7 +323,7 @@ device pci 1d.5 on chip drivers/wifi/generic register "wake" = "GPE0_DW1_01" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[13]" = "1" end # PCI Express Port 14 (x4) diff --git a/src/mainboard/google/puff/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb index b1c50a2..4681e5e 100644 --- a/src/mainboard/google/puff/variants/duffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/duffy/overridetree.cb @@ -455,7 +455,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb index 83f0c16..91d7482 100644 --- a/src/mainboard/google/puff/variants/faffy/overridetree.cb +++ b/src/mainboard/google/puff/variants/faffy/overridetree.cb @@ -429,7 +429,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb index 6458f9f..da76487 100644 --- a/src/mainboard/google/puff/variants/genesis/overridetree.cb +++ b/src/mainboard/google/puff/variants/genesis/overridetree.cb @@ -426,7 +426,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb index 6a2dd7b..19f0823 100644 --- a/src/mainboard/google/puff/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/puff/variants/kaisa/overridetree.cb @@ -455,7 +455,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb index a89c56d..9c6ea64 100644 --- a/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb @@ -428,7 +428,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb index 91a19397..b81c4e4 100644 --- a/src/mainboard/google/puff/variants/noibat/overridetree.cb +++ b/src/mainboard/google/puff/variants/noibat/overridetree.cb @@ -366,7 +366,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb index 3cd6a01..5183202 100644 --- a/src/mainboard/google/puff/variants/puff/overridetree.cb +++ b/src/mainboard/google/puff/variants/puff/overridetree.cb @@ -390,7 +390,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC diff --git a/src/mainboard/google/puff/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb index 5462e9b..4c13e61 100644 --- a/src/mainboard/google/puff/variants/scout/overridetree.cb +++ b/src/mainboard/google/puff/variants/scout/overridetree.cb @@ -406,7 +406,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end end device pci 1c.7 on # PCI Root Port 8 (WLAN) diff --git a/src/mainboard/google/puff/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb index 60ba0bc..de3704c 100644 --- a/src/mainboard/google/puff/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/puff/variants/wyvern/overridetree.cb @@ -391,7 +391,7 @@ register "wake" = "GPE0_DW1_07" # GPP_C7 register "device_index" = "0" register "enable_aspm_l1_2" = "1" - device pci 00.0 on end + device generic 0 on end end register "PcieRpSlotImplemented[6]" = "1" end # RTL8111H Ethernet NIC -- To view, visit https://review.coreboot.org/c/coreboot/+/78870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39 Gerrit-Change-Number: 78870 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/poppy/var/nami: Fix SMBIOS name for Akali360
by Felix Singer (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78876?usp=email ) Change subject: mb/google/poppy/var/nami: Fix SMBIOS name for Akali360 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9b909dba939f726e6fbe71f5b4956b432086029 Gerrit-Change-Number: 78876 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Nov 2023 15:32:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/amd/genoa: Hook SMP and SMM init
by Varshit Pandya (Code Review) 03 Nov '23

03 Nov '23

Attention is currently required from: Arthur Heymans, Felix Held. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76523?usp=email ) Change subject: soc/amd/genoa: Hook SMP and SMM init ...................................................................... Patch Set 5: (4 comments) File src/soc/amd/genoa/include/soc/nvs.h: PS4: > would be good to also split this into a separate patch and add the corresponding asl file in the sam […] Done File src/soc/amd/genoa/include/soc/nvs.h: https://review.coreboot.org/c/coreboot/+/76523/comment/9c4e5e1d_5688189b : PS2, Line 18: uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ : uint8_t lids; /* 0x01 - LID State */ : uint8_t unused_was_pwrs; /* 0x02 - AC Power State */ : uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ > those are likely not needed or used any more. this must still match the corresponding . […] Done https://review.coreboot.org/c/coreboot/+/76523/comment/0acc17f8_738ba485 : PS2, Line 24: uint8_t tmps; /* 0x17 - Temperature Sensor ID */ : uint8_t tcrt; /* 0x18 - Critical Threshold */ : uint8_t tpsv; /* 0x19 - Passive Threshold */ > likely also unused Done File src/soc/amd/genoa/include/soc/smu.h: PS4: > i'd factor out this one into a separate patch that the also selects the smu kconfig option Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76523?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 Gerrit-Change-Number: 76523 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Nov 2023 15:20:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config
by Felix Held (Code Review) 03 Nov '23

03 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78843?usp=email ) Change subject: mb/google/nissa/var/craaskov: Disable storage devices based on fw_config ...................................................................... mb/google/nissa/var/craaskov: Disable storage devices based on fw_config Disable devices in variant.c instead of adding probe statements to devicetree because storage devices need to be enabled when fw_config is unprovisioned, and devicetree does not currently support this (it disables all probed devices when fw_config is unprovisioned). BUG=b:305887856 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/craaskov/Makefile.inc A src/mainboard/google/brya/variants/craaskov/fw_config.c M src/mainboard/google/brya/variants/craaskov/overridetree.cb M src/mainboard/google/brya/variants/craaskov/variant.c 4 files changed, 76 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/craaskov/Makefile.inc b/src/mainboard/google/brya/variants/craaskov/Makefile.inc index f3987ab..7822c45 100644 --- a/src/mainboard/google/brya/variants/craaskov/Makefile.inc +++ b/src/mainboard/google/brya/variants/craaskov/Makefile.inc @@ -3,3 +3,4 @@ ramstage-y += gpio.c ramstage-y += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/brya/variants/craaskov/fw_config.c b/src/mainboard/google/brya/variants/craaskov/fw_config.c new file mode 100644 index 0000000..800fc1f --- /dev/null +++ b/src/mainboard/google/brya/variants/craaskov/fw_config.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index 9cac704..8c29567 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -195,6 +195,14 @@ end end device ref pcie_rp7 off end + device ref emmc on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/brya/variants/craaskov/variant.c b/src/mainboard/google/brya/variants/craaskov/variant.c index 6a79780..68f128c 100644 --- a/src/mainboard/google/brya/variants/craaskov/variant.c +++ b/src/mainboard/google/brya/variants/craaskov/variant.c @@ -1,8 +1,33 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <device/device.h> #include <sar.h> const char *get_wifi_sar_cbfs_filename(void) { return "wifi_sar_0.hex"; } + +void variant_devtree_update(void) +{ + struct device *emmc = DEV_PTR(emmc); + struct device *ufs = DEV_PTR(ufs); + struct device *ish = DEV_PTR(ish); + + if (!fw_config_is_provisioned()) { + printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "eMMC disabled by fw_config\n"); + emmc->enabled = 0; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "UFS disabled by fw_config\n"); + ufs->enabled = 0; + ish->enabled = 0; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/78843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825 Gerrit-Change-Number: 78843 Gerrit-PatchSet: 3 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic
by Felix Held (Code Review) 03 Nov '23

03 Nov '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78873?usp=email ) Change subject: mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic ...................................................................... mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic Change the dGPU/LAN/WiFi device types from PCI to generic, so that the bogus PCI device and function values don't end up in coreboot's internal device tree. The presence of these bogus PCI devices cause the LPI constraint generator to create does a reference for an ACPI device which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a Windows BSOD (INTERNAL_POWER_ERROR). TEST=untested Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/aurash/overridetree.cb M src/mainboard/google/brya/variants/brask/overridetree.cb M src/mainboard/google/brya/variants/constitution/overridetree.cb M src/mainboard/google/brya/variants/gaelin/overridetree.cb M src/mainboard/google/brya/variants/gladios/overridetree.cb M src/mainboard/google/brya/variants/gothrax/overridetree.cb M src/mainboard/google/brya/variants/hades/overridetree.cb M src/mainboard/google/brya/variants/joxer/overridetree.cb M src/mainboard/google/brya/variants/kinox/overridetree.cb M src/mainboard/google/brya/variants/kuldax/overridetree.cb M src/mainboard/google/brya/variants/lisbon/overridetree.cb M src/mainboard/google/brya/variants/marasov/overridetree.cb M src/mainboard/google/brya/variants/moli/overridetree.cb M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/osiris/overridetree.cb M src/mainboard/google/brya/variants/pujjo/overridetree.cb M src/mainboard/google/brya/variants/quandiso/overridetree.cb M src/mainboard/google/brya/variants/xivu/overridetree.cb M src/mainboard/google/brya/variants/yaviks/overridetree.cb M src/mainboard/google/brya/variants/yavilla/overridetree.cb 21 files changed, 26 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/agah/overridetree.cb b/src/mainboard/google/brya/variants/agah/overridetree.cb index 52b9fcd..7bea703 100644 --- a/src/mainboard/google/brya/variants/agah/overridetree.cb +++ b/src/mainboard/google/brya/variants/agah/overridetree.cb @@ -88,7 +88,7 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 alias dgpu on end + device generic 0 alias dgpu on end end device ref dtt on chip drivers/intel/dptf @@ -232,7 +232,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end #RTL8111H Ethernet NIC device ref pcie_rp4 off end diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb index 2b9ebfe..09f7c66 100644 --- a/src/mainboard/google/brya/variants/aurash/overridetree.cb +++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb @@ -163,7 +163,7 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 on end + device generic 0 on end end # IntelI225V Ethernet NIC device ref pcie_rp7 on chip drivers/net @@ -171,7 +171,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 off end #pcie_rp 8 Empty diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 995f20c..a8393b4 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -78,7 +78,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8125 Ethernet NIC device ref pcie4_0 on diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb index c6083f1..41d5022 100644 --- a/src/mainboard/google/brya/variants/constitution/overridetree.cb +++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb @@ -181,7 +181,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8125 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/gaelin/overridetree.cb b/src/mainboard/google/brya/variants/gaelin/overridetree.cb index b3af7c1..d198530 100644 --- a/src/mainboard/google/brya/variants/gaelin/overridetree.cb +++ b/src/mainboard/google/brya/variants/gaelin/overridetree.cb @@ -230,7 +230,7 @@ register "customized_leds" = "0x0843" register "wake" = "GPE0_DW0_07" #GPP_A7 register "device_index" = "0" - device pci 00.0 on end + device generic 0 on end end end #PCIE7 RTL8111K Ethernet NIC device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb index 6a21f2a..0aa0e75 100644 --- a/src/mainboard/google/brya/variants/gladios/overridetree.cb +++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb @@ -190,7 +190,7 @@ register "customized_leds" = "0x060f" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index 87a2b48..e51c1fb 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -330,7 +330,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/hades/overridetree.cb b/src/mainboard/google/brya/variants/hades/overridetree.cb index b8a69a0..53ef892 100644 --- a/src/mainboard/google/brya/variants/hades/overridetree.cb +++ b/src/mainboard/google/brya/variants/hades/overridetree.cb @@ -78,7 +78,7 @@ .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 alias dgpu on end + device generic 0 alias dgpu on end end device ref dtt on chip drivers/intel/dptf @@ -239,7 +239,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end #RTL8111H Ethernet NIC device ref pcie_rp9 on diff --git a/src/mainboard/google/brya/variants/joxer/overridetree.cb b/src/mainboard/google/brya/variants/joxer/overridetree.cb index 187afe5..cfa022c 100644 --- a/src/mainboard/google/brya/variants/joxer/overridetree.cb +++ b/src/mainboard/google/brya/variants/joxer/overridetree.cb @@ -326,7 +326,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 off end # PCIE7 no SD card diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index fcca3d8..71d0e27 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -247,7 +247,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" @@ -278,7 +278,7 @@ register "wake" = "GPE0_DW0_07" #GPP_A7 register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/kuldax/overridetree.cb b/src/mainboard/google/brya/variants/kuldax/overridetree.cb index a6adecf..6db03ac 100644 --- a/src/mainboard/google/brya/variants/kuldax/overridetree.cb +++ b/src/mainboard/google/brya/variants/kuldax/overridetree.cb @@ -207,7 +207,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8125 and RTL8111K Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 6a21f2a..0aa0e75 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -190,7 +190,7 @@ register "customized_leds" = "0x060f" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111 Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index 7fd0ef1..311971f 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -318,7 +318,7 @@ }" chip drivers/wifi/generic register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp8 off end diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index e636540..5397463 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -164,7 +164,7 @@ .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - device pci 00.0 on end + device generic 0 on end end # IntelI225V Ethernet NIC device ref pcie_rp7 on chip drivers/net @@ -172,7 +172,7 @@ register "wake" = "GPE0_DW0_07" register "device_index" = "0" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end # RTL8111K Ethernet NIC device ref pcie_rp8 on diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index 9d9b871..5de5c1b 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -209,7 +209,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pch_espi on diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb index 650d508..5ba725b 100644 --- a/src/mainboard/google/brya/variants/osiris/overridetree.cb +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -281,7 +281,7 @@ register "customized_led2" = "0x028" register "enable_aspm_l1_2" = "1" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end # Enable PCIE 7 using clk 6 register "pch_pcie_rp[PCH_RP(7)]" = "{ diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 51383e0..59ab871 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -673,7 +673,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index e94d3da..64cd862 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -398,7 +398,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb index be4d8df..2e781a2 100644 --- a/src/mainboard/google/brya/variants/xivu/overridetree.cb +++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb @@ -376,7 +376,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/yaviks/overridetree.cb b/src/mainboard/google/brya/variants/yaviks/overridetree.cb index 308ed10..580181c 100644 --- a/src/mainboard/google/brya/variants/yaviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/yaviks/overridetree.cb @@ -450,7 +450,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 on diff --git a/src/mainboard/google/brya/variants/yavilla/overridetree.cb b/src/mainboard/google/brya/variants/yavilla/overridetree.cb index ee5a3b6..4a96742 100644 --- a/src/mainboard/google/brya/variants/yavilla/overridetree.cb +++ b/src/mainboard/google/brya/variants/yavilla/overridetree.cb @@ -496,7 +496,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" - device pci 00.0 on end + device generic 0 on end end end device ref pcie_rp7 off end #PCIE7 no SD card -- To view, visit https://review.coreboot.org/c/coreboot/+/78873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1 Gerrit-Change-Number: 78873 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2023